UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - D1.7 -

2-digit multiplexed 7-segment display

Products

D1.6

D1.8

1.- Specifications

We want to use the same 7-segment decoder function for driving multiple common-anode displays. To keep it simple, we implement only a 2-digit multiplexed 7-segment display circuit. In this way, we will multiplex the information to be represented between Digit 1 and Digit 0. As seen in Fig. 1, only one display is active at a given time controlled by input D. 

Using the same principle, it is easy to imagine how to expand the circuit for driving a larger number of common-anode 7-segments displays.

This Hex_7seg_MUX_2digit.pdsprj simulation in Proteus, give you a better idea how the multiplexer works. 

2-digit 7-segment display multiplexed system

Fig.1. Symbol of Hex_7seg_MUX_2digit.

Complete the symbol in Fig. 1 and the circuit's truth table in Fig. 2 adding a new input E (enable) that blank the two digits when active.

Truth table

Fig.2. Initial idea of the circuit truth table.

Draw an example of timing diagram to be used later as stimulus in the VHDL testbench when verifying the synthesised circuit. Consider Min_Pulse = 7.45 ms.

The same project B3.7 is proposed in Chapter 3 for learning the basics of μC software organisation and basic digital I/O.

 

CPLD or FPGA target chip options:

 Target option #1.: MAX II

 Target option #2.: MAX 10

 Target option #3.: Cyclone IV

 

2. Planning

Plan A structural circuit based on logic gates and equations in a single VHDL file. We have many strategies, for instance:

option #1: use minilog to obtain PoS.

In the highlighted project P2 you have an example of an HEX to 7-segment decoder.

Project location:

 C:\CSD\P2\Hex_7seg_MUX_2digit_PoS\(files)

 

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

option #2: use minilog to obtain SoP.

In the highlighted project P2 you have an example of an HEX to 7-segment decoder.

Project location:

 C:\CSD\P2\Hex_7seg_MUX_2digit_SoP\(files)

In the highlighted project P2 you have an example of an HEX to 7-segment decoder.

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

Plan B behavioural approach writing the truth table or the high-level description or algorithm in VHDL in a single file (flat).

In the tutorial DT2.6 you can find an example of similar HEX to 7-segment decoder.

Project location:

 C:\CSD\P2\Hex_7seg_MUX_2digit_B\(files)

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

After having studied P4 tutorials, additional questions can be added to our report. For instance: