UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - D1.6 -

Water tank level meter

Products

D1.5

D1.7

1.- Specifications

Design the circuit Tank_level_meter represented in Fig. 1 studing and adapting ideas from the L2.5 lecture on incomplete truth tables.

The same project B3.6 is proposed in Chapter 3 for learning the basics of μC software organisation and basic digital I/O.

tank schematic

Fig.1. The tank level meter idea built using digital optical sensors (1), (2) attached to  the tank wall. 

Draw an example of timing diagram to be used later as stimulus in the VHDL testbench when verifying the synthesised circuit. Consider Min_Pulse = 5.21 ms.

CPLD or FPGA target chip options:

 option #1.: MAX II

 option #2.: MAX 10

 option #3.: Cyclone IV

 

2. Planning

Plan A structural circuit based on logic gates and equations in a single VHDL file. We have many estrategies, for instance:

option #1: use minilog to obtain PoS.

Project location:

 C:\CSD\P2\Tank_level_meter_PoS\(files)

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

option #2: use minilog to obtain SoP.

Project location:

 C:\CSD\P2\Tank_level_meter_SoP\(files)

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

Plan B behavioural approach writing the truth table or the high-level description or algorithm in VHDL in a single file (flat).

Project location:

 C:\CSD\P2\Tank_level_meter_B\(files)

 

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

Plan C2 is a hierarchical architecture based (multiple VHDL file) on components and signals. For instance, how can you chain three 3-sensor level meters to obtain this 9-sensor level meter?

 C:\CSD\P2\Tank_level_meter_C2\(files)

 

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

After having studied P4 tutorials, additional questions can be added to our report. For instance: