After studying the content of these projects, you will be able to:

• Discuss the standard architecture of a finite state machine (FSM): current and next states, the state register, the output logic (CC2) and state logic (CC1) combinational circuits.

• Describe the truth table of the output logic circuit (CC2) and find its behavioural interpretation (flow chart).

• Describe the truth table of the state logic circuit (CC1) and find its behavioural interpretation (flow chart or algorithmic state machine [ASM] chart).

• Explain the specifications of the system: symbol, inputs and outputs, number of states and state transitions, state encoding (binary sequential, Gray, one-hot, etc.), state register (number of D_FF used in the design).

• Develop the FSM hierarchical structure in a single VHDL file (plan  C1) and synthesise a project targeting a PLD.

• Run functional and gate-level simulations to test and verify the FSM performance.

• Mesure the CLK to output propagation time (tCO) and the maximum speed of a FSM.

• Design simple FSM using the CSD systematic methodology: from the specifications to the final verification and prototyping. For instance: traffic light sequencers, light control systems, matrix keypad encoders, step motor controller, push-button debouncer and synchroniser, etc.