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Adder_1bit plan C2: structural hierarchical multiple-file VHDL |
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Example on how to use MoD for implementing logic functions
1. Specifications
Design a 1-bit adder using a hierarchy of components based on method of decoders discused in L3.3.
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Fig. 1. Symbol and truth table of a 1-bit adder circuit. It is also called full adder. |
This in Fig. 2 is a simple sketch that represents the truth table in time. The idea of applying input vectors that can be any binary combination.
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Fig. 2. Timing diagram where all the inputs are applied sequentially and hence, the output is predicted accordingly to the truth table. |
2. Planning
The VHDL file will be named Adder_1bit.vhd, the same name given to the entity. The project name is Adder_1bit_prj.
Plan C2) Building blocks (hierarchical structure , multiple-file project):
- Plan using MoD to implement logic functions.
This project will be located at:
C:\CSD\P3\Adder_1bit_MoD\(files)
3. Developing the project using EDA tools
The top entity Adder_1bit.vhd, and the Dec_3_8 internal component using a plan B description (that you see, it is a project in itself).
Target chip: MAX10 10M50DAF484C7
RTL and technology schematics.
4. Testing and validating the design
An example test bench Adder_1bit_tb.vhd. Run the VHDL simulation EDA tool to obtain and discuss the timing diagram. Remember that from the testing point of view, even if you have designed the Adder_1bit using several plans, you can use all the time the same testbench.
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Fig. 4. Example testbench showing results |
5. Report
Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources.
Follow this rubric for writing reports.
6. Prototyping
Use training boards and perform laboratory measurements to verify how the circuit works.