After studying the content of these projects, you will be able to:

• Explain the TMR0 architecture and how to configure it for timing and counting applications.

• Deduce the timing period (TP) design equation and how to generate an arbitrary large counting modulo including RAM memory post-scalers.

• Determine for the TMR0 the systematic software overhead when timing.

• Explain the TMR2 architecture and how to comfigure it for precision timing applications.

• Explain how to adapt applications based on dedicated processor architectures (L8.1) to microcontrollers.