UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

BCD to binary radix-2 modulo 40. Plan B: behavioural single-file VHDL

P2

Type 74184 standard commercial chip

1. Specifications

Design a classic chip like the DM74184 using plan B structural approach.

Symbol adaptation

Fig. 1. BCD_bin_mod40 symbol adapted from the chip DM74184. When the chip is desabled, we will implement the code "111111". We can imagine the circuit truth table either using plan A minimised equations or copying directly the truth table using a plan B schematic. This chip is capable of converting any BCD number from '00' to '39' to 6-bit binary radix-2. Inputs T(1..0), U(3..0); output B(5..0).

The circuit truth table, adapting input and output names to CSD style is shown in Fig. 2. 

Truth table

Fig. 2. BCD_bin_mod40 component truth table. Adapted from the DM184 datasheet. This chip is capable of converting any BCD number from 0 to 39 into binary radix-2. This is why we name it modulo 40.

Draw the sketch of a timing diagram to demonstrate how the circuit works for several input stimulus.

Timing diagram sketch

Fig. 3. Example timing diagram.

 

This is the article from Wikipedia: the reverse double dabble algorithm is used to convert BCD numbers into binary radix-2.

 

Optional: How to add a new output Error that is '1' when one illegal code is pressed?

 

2. Planning

Our circuit can be implemented translating the truth table in Fig. 2 using plan B. Draw a flow chart schematic to be able to use the truth table artefact.

High level interpretation of the truth table
Fig. 4. High-level schematic ready for VHDL translation. The truth table artefact will cover 64 combinations.

 Project and file locations:

C:\CSD\P2\BCD_bin_mod40/(files)

 

3. Development

Find a similar VHDL description for a plan B circuit, copy and adapt. This is the schematic in Fig. 4: BCD_bin_mod40.vhd

Entity definition in VHDL
Fig. 5. Entity definition is the same whatever the plan.

Start an EDA synthesis project named BCD_bin_mod40_prj for a given target chip, for example Intel MAX II EPM2210F324C3 and examine results.

RTL view

Fig. 6. RTL schematic of the BCD_bin_mod40 using high-level descrition.

Technology view schematic.

Tecnology map

Fig. 7. Technology view of BCD_bin_mod40 targeting Intel CPLD: EPM2210F324C3. The Chip Planner tool in Quartus Prime can be used to locate exactly where your circuit is synthesised in the CPLD lattice of logic cells.

 

4. Testing

In Fig. 8 is represented the testbench schematic to stimulate the unit under test (UUT) with input vectors. In a step #1 generate the skeleton of the testbench file, in a step #2 add stimulus translating to VHDL input activity from the time diagram in Fig. 2. This is an example of a simple test bench BCD_bin_mod40_tb.vhd from which you can copy the constant Min_Pulse and the stimulus process.

Testbench fixture

Fig. 8. Testbench fixture to verify that our circuit works as expected. 

Start the VHDL simulator project, BCD_bin_mod40_functional_sim,  and run the test. Verify applying sufficient test vector that the device works as expected (verify how the information of each channel is selected). Print timing diagram screen and add comments on the signals to show how the device works.

Functional simulation
Fig. 9. Waveform results from the logic analyser. 

 

5. Report

 

6. Prototyping

 

Annex  A: DM184 functions

Design the DM184 component to be used as building block for larger BCD to binary radix-2 converters, as proposed in D1.15.