Chapter II Finite state machines (FSM)

Unit 2.1. Writing technical reports and delivering oral presentations

Unit 2.2. The architecture of a canonical synchronous Finite State Machine (FSM)

Unit 2.3. Designing a cascadable 4-bit binary counter using the FSM architecture

Unit 2.4. Designing a T-type flip flop (T-FF). A frequency divider by 2. A pulse to square wave converter.

Unit 2.5. Frequency dividers: generating a set of synchronous clock signals from a crystal oscillator (CC1 using the ARITHMETIC library)

Unit 2.6A. Gate-level simulation of synchronous systems using ispLEVER/Synplify and ActiveHDL using TCL do macro and VHO + SDF files.

Unit 2.6B. Gate-level simulation  of synchronous systems using Quartus-II and ModelSim Altera Starter using Tool Command Language (TCL) do macro and VHO + SDO files.

Unit 2.6C. Gate-level simulation  of synchronous systems using Xilinx ISim and VHDL test bench

Unit 2.7. Designing data registers using the FSM architecture

Unit 2.8. Filtering and synchronising inputs: A pushbutton debouncer circuit

Unit 2.9. Synthesised FSM using different coding attributes: sequential, one-hot, gray, etc..

Unit 2.10. Designing shift registers

Unit 2.11. Designing read/write data memories