-------------------------------------------------------------------------------- -- Tutorial P3 on the design of an adaptation of the standard chip 74LS47: -- decoder for hexadecimal to 7-segment with blanking control signals -- Structural approach, plan C2. We take advantage of the similar circuit -- HEX_7SEG_DECODER designed in P2 using it as a component. -- The extra logic is for implementing additional control inputs and outputs -- The design plan translated here to VHDL is at this page: -- https://digsys.upc.edu/csd/units/DE10_Lite/DE10_Lite.html#plan ------------------------------------------------------ -- UPC - EETAC - CSD -- http://digsys.upc.edu -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY Dec_hex_7seg IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); BI_L, LT_L, RBI_L : IN STD_LOGIC; RBO_L : OUT STD_LOGIC; Y_L : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END Dec_hex_7seg; ARCHITECTURE hierarchical_structure OF Dec_hex_7seg IS -- Components to be used: COMPONENT HEX_7SEG_DECODER IS -- From P2 tutorial PORT ( X_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); BI_L : IN STD_LOGIC; A_L, B_L, C_L, D_L, E_L, F_L, G_L : OUT STD_LOGIC ); END COMPONENT; -- Signals, -- The wires to connect the modules: SIGNAL Z_L, C0, C1 : STD_LOGIC; SIGNAL P, Q : STD_LOGIC_VECTOR (6 DOWNTO 0); BEGIN -- Component instantiation: Chip1 : HEX_7SEG_DECODER PORT MAP ( -- from component name => to signal or port name X_IN => D, BI_L => BI_L, A_L => P(0), B_L => P(1), C_L => P(2), D_L => P(3), E_L => P(4), F_L => P(5), G_L => P(6) ); -- Other circuits and equations: Y_L(6) <= Q(6) and C1; Y_L(5) <= Q(5) and C1; Y_L(4) <= Q(4) and C1; Y_L(3) <= Q(3) and C1; Y_L(2) <= Q(2) and C1; Y_L(1) <= Q(1) and C1; Y_L(0) <= Q(0) and C1; Z_L <= D(3) or D(2) or D(1) or D(0); C0 <= not(BI_L) or (BI_L and LT_L and not(Z_L) and not(RBI_L)); C1 <= not(BI_L) or LT_L; RBO_L <= not(C0); Q(6) <= P(6) or C0; Q(5) <= P(5) or C0; Q(4) <= P(4) or C0; Q(3) <= P(3) or C0; Q(2) <= P(2) or C0; Q(1) <= P(1) or C0; Q(0) <= P(0) or C0; END hierarchical_structure;