upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

List of preparatory laboratory assignments  (PLA)


NOTE: This page shows several PLA projects from former CSD courses. In this way, you get and idea on the type of designs that we'll develop this semester.  

NOTE: All the projects about combinational circuits (chapter 1) and sequential systems (chapter 2) for this semester 1920-Q2 has to be developed and testes using Intel Quartus Prime Lite EDA tools.

NOTE: We'll try to discuss and solve the PLA as scheduled, even if the due date is delayed because of the special circumstances.

 

PLA#1.1 on the design of standard logic circuits 

Individual. Due date for the next Lab #4 (delayed to April 17th)

Specify, plan, develop and test the Problem 2.6, a wind direction compass based on a combinational circuit.

This is a sample template  to organise your report.

- Section 1 (4p): Specifications and questions from 1 to 11. This is Proteus circuit for experimenting. This is an example truth table deduced playing with the circuit and studying the Fig. 17.

- Section 2 (1p): Choose a plan for the wind_meter chip (each cooperative group member will be given a plan):

- Plan A (12). Project location L:\CSD\P2\wind_compassA\wind_compass.vhd

- Plan B (13). Project location L:\CSD\P2\wind_compassB\wind_compass.vhd

- Sections 3 (2.5p): Develop (14). Quartus Prime Intel Edition. Target chip: the Cyclone IV EP4CE115F29C7N in the DE2-115 board. Some introductory insight in PLD.

- Section 4 (2.5p): Test and verify (15). wind_compass_tb.vhd. ModelSim Intel Starter Edition.

You can capture the screen of the timing diagram or anythin else using the "Snipping Tool" or similar. For instance you can buy this commercial Snagit software for a very affordable cost and use it for all your studies. 

NOTE: The use of the software available in the VD and the lab C4-129B is recommended. However, only 18 sessions can run concurrently and perhaps the system colapses approaching deadlines, thus, you must make a reservation to use the laboratory C4-129B as long as you like for the whole semester. Another option only for Chapters I and II (from P1 to P8) is to download and install in your own PC the free edition of Quartus Prime registering as a UPC student in the Intel web. Tell us if you like to do so.

PLA#1.2 on the design of arithmetic circuits and propagation time measurement

Teamwork in cooperative groups. Due date for the next Lab #6 (delayed to April 17th)

Complete the circuit named Selectable _add_subt_comp_12bit represented in Fig. 1.  Many schematics and diagrams for adding, subtracting and comparing both, radix-2 and integers (2C) are available in P3 and P4.

Symbol 
Fig. 1. The entity symbol for the PLA#1.2.

This is a sample template to organise your report.

The main idea behind this hierarchical design is, once the project has been understood (top --> botom), let us proceed from bottom --> top solving several subprojects to design the required components in each architectural layer.

For example, the comparator subsection of the project can be subdivided in:

Project 1) [Project E. Due date April 3] Solve as usual (S, P, D, T) the component Comp_1bit as stated beow for even and odd laboratory teams:

  • Even cooperative groups: solve the component Comp_1bit using plan A and only_NAND equations.

  • Odd cooperative groups: solve the component Comp_1bit using plan B. Be aware that because this is a combinational circuit, whatever to be translated to VHDL to synthesise has to generate an RTL schematic with no inferred latches or memory devices (examine the synthesis report).

Remember as well that the 1-bit comparator is solved in two tutorials in different fashions: Comp_1bit following a plan A with SoP equations, and Comp_1bit using the plan C2 and the MoM. If you don't find the solution to this Prject 1, copy the tutorials in order to go ahead with the next project.  

Project 2) Solve the Comp_12bit. Natural (whole) numbers in radix-2. This is an idea of a plan for N = 10.

Project 3) Solve the Int_comp_12bit for integers in 2C. This is an idea on how to deduce an algorithm and therefore the final plan for N = 8.

Project 4) Solve the Selectable_comp_12bit as in problem 4.3 which is for 10 bit comparisons. The input N decides which data type to compare: natural or integer numbers. This is the conceptual idea (10 bit) of a circuit for two data types. Ths is how the final plan (10 bit) may look like if only one Comp_12bit is desired for both, radix-2 numbers and signed integers?

For example, the adder and subtractor can be subdivided in:

Project 5)  [Project F. Due date April 4]

  • Solve as usual (S, P, D, T) the project Int_add_subt_12bit inventing a plan C2. In digsys pages you can find similar circuits like the Adder_10bit developed in the Lab#5 session and the Int_add_subt_8bit from P4. Integers are encoded in 2C.

  • Compare results from gate-level simulations and timing analyser, measuring propagation delays an calculating the maximum speed of computing when sinthesising the project for both: a CPLD MAX II EPM2210F324C3, and an FPGA Cyclone IV EP4CE115F29C7N. Which one is faster?

Project 6)   Solve the project Selectable_add_subt_12bit. The input N decides which data type to add or subtract: natural or integer numbers. This is the conceptual idea and a possible plan.

And, finally, combine the selectable comparator and adder-subtractor in the entity represented in Fig.1: 

Project 7)  Solve the project Selectable_add_subt_comp_12bit. Which is the maximum speed of computing of this circuit when synthesised for a target FPGA Cyclone IV EP4CE115F29C7N?

Solving projects in cooperative groups is not easy, on the contrary. Thus, clarify which task each team mate has to do and is responsible for, in which time the task has to be done, and how are you assuring that everybody learns all the project sections.

Discuss extensively the problem (specifications and plan) with your team mates and instructors using pen & paper and some numbers to test before starting the developing and verification using the EDA tools. Remember that the VHDL has no value unless there is a detailed original plan.

PLA#2.1 on 1-bit memory cells and FSM

 

 

PLA#3.1 on microcontroller circuits

 

Final P_Ch3, report + oral presentation