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List of preparatory laboratory assignments  (PLA)


PLA#1.1 on the design of standard logic circuits 

Individual for the next Lab #4 (due date 07/10):

Specify, plan, develop and test the Problem 2.6, a wind direction compass based on a combinational circuit.

This is a sample template to organise your report.

- Section 1 (4p): Specifications and questions from 1 to 11. This is Proteus circuit for experimenting. This is an example truth table deduced playing with the circuit and studying the Fig. 17.

- Section 2 (1p): Choose a plan for the wind_meter chip (each cooperative group member will be given a plan):

- Plan A (12). Project location L:\CSD\P2\wind_compassA\wind_compass.vhd

- Plan B (13). Project location L:\CSD\P2\wind_compassB\wind_compass.vhd

- Sections 3 (2.5p): Develop (14). Xilinx ISE, target chip: Spartan-3E XC3S500E-FG320

- Section 4 (2.5p): Test and verify (15). wind_compass_tb.vhd. ISim Xilinx ISim. You can capture the screen of the timing diagram using the "Snipping Tool" or similar.

 

PLA#1.2 on the design of arithmetic circuits and propagation time measurement

Teamwork in cooperative groups for the next Lab #6 (due date 21/10):

complete the circuit named Selectable _add_subt_comp_10bit represented in Fig. 1. Remember that the Comp_1bit is completely developed in its tutorial using the plan A and SoP. Many other files for adding and subtracting are available in P4 and P3.

Selectable circuit

Fig. 1. The entity for the PLA#1.2.

This is a sample template to organise your report.

The main idea behind this hierarchical design is, once the project has been understood top --> botom, to proceed bottom --> top solving several subprojects to design the required components in each architectural layer.

For example, the comparator subsection of the project can be subdivided in:

Project 1) Solve as usual (S, P, D, T) the component Comp_1bit as stated above for even and odd groups. I you don't find the solution, copy the SoP files from the Comp_1bit tutorial to go ahead with the next project. 

Project 2) Solve the Comp_10bit. Natural (whole) numbers in radix-2. This is an idea of a plan.

Project 3) Solve the Int_comp_10bit for integers in 2C. This is an idea on how to deduce an algorithm and therefore the final plan.

Project 4) Solve the Selectable_comp_10bit in problem 4.4. The input N decides which data type to compare: natural or integer numbers. This is the conceptual idea of a circuit for two data types. How the final plan may look like if only one Comp_10bit is desired?

For example, the adder and subtractor can be subdivided in:

Project 5)  Using the Adder_10bit developed in Lab#5 session and the Int_add_subt_8bit from P4, solve the project Int_add_subt_10bit. Integers in 2C.

Project 6)  Solve the project Selectable_add_subt_10bit. The input N decides which data type to add or subtract: natural or integer numbers. This is the conceptual idea and a possible plan.

And, finally, combine the selectable comparator and adder-subtractor in the entity represented in Fig.1: 

Project 7)  Solve the project Selectable_add_subt_comp_10bit.

Solving projects in cooperative groups is not easy, on the contrary. Thus, clarify which task each team mate has to do and is responsible for, in which time the task has to be done, and how are you assuring that everybody learns all the project sections.

Discuss extensively the problem (specifications and plan) with your team mates and instructors using pen & paper and some numbers to test before starting the developing and verification using the EDA tools. Remember that the VHDL has no value unless there is a detailed original plan.

 

Note: The measurement of the operational speed of the synthesised circuit can be performed in any of previous projects using the gate-level simulator.

 

PLA#2.1 on 1-bit memory cells and FSM

Individual for the next Lab #8 (due date 18/11):

The task is for solving an analysis based on FF and also for designing a project using the FSM strategy.

Analysis. Each team member has been assigned a problem 5.3, 5.4, 5.7 or 5,8 to solve (3p)

NOTE 1: Do not solve the problem many questions but simply deduce the timing diagram. This means for you take our position as a lecturer and being able to explain how to deduce the timing diagram to 40 people in class (so, you need class notes, slides, diagrams, and a sequence of steps to make the problem comprehensible to other students like you).

NOTE 2: One way to tackle the problem solution, because most of the circuits have several CLK signals, may be:  1) Study a single flip-flop and deduce its timing diagram; 2) connect two flip-flops in a way that you have two CLK signals and try to deduce the timing diagram; 3) now, go for your circuit. Check your solution with Proteus results (those are circuits in Proteus that can be modified conveniently).

Project. Solve the problem 6.6 on a water tank controller (7p). This is the discussion of the state diagram.

This is a sample template to organise your individual report.

 

PLA#2.2 on counters and registers

Teamwork for the next Lab #10 (due date 2/12):

Problem 8.4 specifications. This is a suggested plan organising the system as a dedicated processor. This is a suggested state diagram that can be inferred for the control unit. NOTE that this documents and discussions are subjected to changes and improvements in a way that you acquire a better idea of what is on stake in the whole design process.

Draw a timing diagram for the Counter_mod50 component. This is a timing diagram for the JK_FF in the context of this project. Realise that now these devices will be commaded by orders form the control unit. The ROM_128x8 component can be solved as Plan B like in the tutorials in P5: Method of ROM for implementing combinational circuits.

This is a sample template to organise your report.

Please, maximase your chances for getting better grades, learn from your previous experience solving projects in cooperative groups: which you know that it is not an easy task: discuss extensively the problem (specifications and plan) with your team mates and instructors using pen & paper before starting the developing and test. And clarify which job does each team mate and how are you assuring that everybody learns all the project sections.

As you can see, for simplicity reasons a single CLK is used for both running the counter operations and driving the control unit. An enhanced design can have two clock signals: one for running the operations in the datapath, and another for managing the control unit FSM. In this type of systems the necessary CLK signals can be derived fron a single high frequency quartz oscillator using a CLK_Generator circuit as explained in P8. In this problem a single CLK signal of 5 Hz is required (for instance dividing by 1e+7 a 50 MHz oscillator).

(Optional) Design a ST start/stop button debouncing filter as in this P6 tutorial, and also a CLK_generator in order to download the design in a target PLD chip populating a prototyping board from Lattice Semiconductor, Intel-Altera or Xilinx.

 

 

PLA#3.1 on microcontroller circuits

Individual for the next Lab #12 (new deadline is January 10th, before 12 p.m.)

Problem 9.4: Solve an 12-to-4 encoder with binary and 7-segment outputs to represent the results. A similar entity can be studied in P2 encoders.

Each team member has been assigned an option for connecting inputs/outputs to the chip port pins. 

This is a sample template to organise your plan and report. And, in P9 there is the complete example Adder_BCD_1digit with 7-segment display that can be studied and adapted to this new Enc_12_4.

HINT: Some ideas on how to start the solution once you have completely studied the specifications and organized you plan:

1) Copy the adder hardware file to the new location (for example L:\P9\Enc_12_4\(files) ) and rename it Enc_12_4.pdsprj

2) Copy the adder code to the new location and rename it Enc_12_4.c

3) Generate a new MPLABX project naming it Enc_12_4_prj targeting the PIC18F4520

4) Assign the cof to the hardware while keeping both applications working concurrently and run.

5) Now the process is to start making modifications to both hardware and software one at a time  and run and test watching the variables of interest. This is an example circuit. Comment all the code in truth_table() and write_outputs() leaving only what is of interest for reading Ei_L in read_inputs() and init_system(). Simply connect Ei_L pin and nothing else until you can watch the variable var_Ei (active high) running live, meaning var_Ei = 0b00000001 when clicked and  var_Ei = 0b00000000 when released.

6) Continue working only in the read_inputs() to capture the D_L(11..0), if not all of them, only with the ones connected at the same port. Your objective is to watch the int variable var_D active high. An idea is to leave the priority to the end, as a second phase, when your  system is already working clicking a key at a time. Your aim is to click a key, for example the 9, and obtain the variable var_D = 0b0000001000000000 in the watch window. This is an example of changing the variable type from char to int.

7) And so on, now with the truth table to deduce the var_Y from the var_Ei and var_D inputs, probably using a behavioural flowchart approach. The truth table can also be subdivided in two sections as you have seen in the example: first obtaining var_Y, var_Eo and var_GS; and later, the var_S.

8) Finally, go solving write_outputs() pin by pin as in the examples. And be aware that all this micro-steps have to be done running a watching with both concurrent applications running.

--> By Monday 23rd, I'll be in lab C4-129B from 11h to 13h, in case you like to ask questions.

 

Final P_Ch3, report + oral presentation

Teamwork for the next due date 17/01/20, 12:00

P_Ch3: Each team has selected a project:

3T11: MG01 -- > N5; MG02 -- > N11; MG03 -- > N4; MG04 -- > N14;  MG05 -- > ?;  MG06 -- > N7;  MG07 -- > ?

3T12: MG08 -- > N15;  MG09 -- > N12;  MG10 -- > N06;  MG11 -- > N2;  MG12 -- > N1;  MG13 -- > N9;  MG14 -- > N5; MG15 -- > ?

3T21: G01--> N11; G02--> N23; G03--> N5; G04--> N12; G05--> N15; G06--> N3; G07--> N14; G08--> N21

3T22: G11--> N11; G12--> N15; G13--> N24; G14--> N12