UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


Planning lectures and labs  (21-22 Q2)


Chapter 1: Combinational circuits
W1 L1.1 L1.2 L1.3 L1.4 L1.5                  
W2 L1.6 L2.1 L2.2   LAB1_1 P_Ch1 SP1_1            
W3     L2.3 L2.4 L2.5   LAB1_2 SP1_1 SP1_2          
W4       L3.1 L3.2 L3.3   LAB2 SP1_2   SP1_3      
W5 L4.1 L4.2 L4.3 LAB3 SP1_3 SP1_4
W6                     LAB4 SP1_4 P_Ch1 Q1-4



Fig. 1. Symbol of a generalised  combinational circuit. This block is described by its truth table or the equivalent canonical equations product of maxterms or sum of minterms.


Chapter 2: Sequential systems
W6 L5.1 L5.2 L5.3     P_Ch2 SP2_1              
W7   L5.4 L6.1 AR1    LAB5 SP2_1   SP2_2          
Midterm exam
W8   L6.2                         
W9 L7.1 L7.2 L7.3   LAB6 SP2_2 SP2_3
W10           L8.1 L8.2   LAB7 SP2_3 SP2_4      
W11                     SP2_4 P_Ch2   Q5-8


Fig. 2. Internal architecture of a synchronous canonical finite state machine as studied in CSD.

The state register contains a bank of r D_FF memory cells.  r depends on state coding style.

The  FSM, even if structured in three blocks,  is implemented in a single VHDL file (the only time where plan C1 is used in CSD).

Chapter 3: Microcontrollers
W10 L9.1                          
W11   L9.2 L9.3 L9.4   LAB9   P_Ch3 SP3_1
W12     L10.1 L10.2 L11   LAB10   SP3_1 SP3_2        
W13 L12.1 L12.2 L12.3  LAB11 SP3_2 SP3_3
W14 AR2 AR3 LAB_AR SP3_3 P_Ch3 Q9-12

Software structure 

  Fig. 3. The key concept in Chapter 3 is adapting the FSM structure to software environment in C language. Our programming style and code organisation will mimic concepts studied in previous chapters.

Former lab projects (1), (2), (3), (4), (5), (6)