P_Ch2 Lab9	P_Ch3: Designing a microcontroller application based on FSM architecture	SP3_1 Planning

NOTE: EDA in use this semester: Proteus electrical simulator, Notepad++ editor, Microchip MPLABX and XC8 compiler.

1. Specifications

The aim of this project is to reinvent the digital programmable timer Prog_Timer following similar specifications and planning ideas presented in P_Ch2. Therefore, we  will emphasise how an application is adapted to C language and microcontrollers in comparison on how it was engineered previously to hardware design.

Fig. 1. Symbol of the final Prog_Timer as solved in design phase #3.

Features:

• Timed output signal Timer_out maximum timing period = 65535 ms

• Programmable 16-bit pulse count (PC)

• End of timing period pulse (ETP) width = 50 ms

• Active-high interrupt-driven TRG pulse. Non-retriggerable, meaning that other trigger pulses are ignored while the device is on duty.

• Asynchronous reset (CD)

• LCD display for representing ASCII messages indicating timer operation

• Microchip PIC18F4520 microcontroller chip

• Dedicated processor architecture adapting concepts from P_Ch2 planning in successive phases:

  • Design phase #1: External CLK time-base of 1 KHz

  • Design phase #2: LCD display

  • Design phase #3: TMR0 time-base from μP 16 MHz crystal oscillator OSC

Fig. 2. Example of waveforms in design phase #1 where an external CLK source is used as time-base. A TRG pulse, for instance clicking a button, triggers the timing period. Once the timing period (TP) ends, a single pulse of 50·TCLK duration is generated to indicate that the device will be back to idle and can be used again for programing any other timing interval.

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Extra features may be added optionally introducing new design phases once the basic project is complete and operates correctly. For instance: Retriggerable switch to be able to generate arbitrary large timing periods, TMR2 instead of TMR0 to obtain higher precision, alarm sound to indicate end of timing period, serial (RS232) or keypad pulse count PC programing, selectable time scale: 1ms, 100 ms, 1s, etc.

 

2. Planning

Planning several design phases (subprojects):

SP3_1

Due date May 24

On basic digital I/O

SP3_2

May 31

Prog_Timer design phase #1: Adapting FSM to μC using external interrupts.

SP3_3

June 10

Prog_Timer design phase #2: peripheral LCD

P_Ch3

June 10

Prog_Timer phase #3: TMR0 time-base

Q&A

 

To make P_Ch3 simple and reasonable in the given time constraints and be able to embed its design within CSD course timeline, we propose adapting to uC the architecture designed in P_Ch2 by means of successive design phases introducing one new feature at a time.

• SP3_1 is used to comprehend how basic I/O works. init system(), read_inputs(), write_outputs(). We will design a combinational circuit such Comp_4bit

• SP3_2 Prog_Timer design phase #1 implement the FSM and datapath using RAM variables and external interrupts ISR().

• SP3_3. Prog_Timer_LCD design phase #2 adding an LCD for displaying ASCII messages or even numerical time data.

• P_Ch3. Prog_Timer_LCD_TMR0 design phase#3: the complete design will replace the external CLK generating the time-base using the embedded TMR0 peripheral.

 

3. Developing and testing

The development and test of P_Ch3 implies solving each subproject beforehand and the final programing in C language of the complete system Prog_Timer_LCD_TMR0.

In Chapter 3 testing is interactive using Proteus while programming and debugging C code step by step. 

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4. Reporting

Marking grid

Work assessments to be carried out in laboratory sessions:
	SP3_1	SP3_2
	1p	1p

Note Work assessment in lab sessions is Individual

 

P_Ch3 handwritten report and video presentation:
SP3_1	SP3_2	SP3_3	Video	P_Ch3
1p	1p	2p	2p	2p

Notes on lab assessment: student grades are not simply reflecting report or video quality, but implicitly, they include laboratory participation, questions and answers, problem solving skills, attendance and punctuality, active attitude and group work.

For instance, SP3_1 annex in PDF report may be a group submission including improvements on SP3_1 materials discussed during lab work assessments.

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Follow this rubric for writing reports.

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Former lab projects (1), (2), (3), (4), (5), (6)

 

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