UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

P_Ch1

Lab4

P_Ch2: Designing sequential systems: programmable timer

SP2_1

P_Ch3


1. Specifications

The aim of this project is to invent a digital programmable timer (Prog_timer) as shown in Fig. 1.

Features:

Symbol
Waveforms

Fig. 1. Symbol and port description for the entity to be designed. A pulse, for instance clicking a button, triggers the timing period. Once the timing period (TP) ends, a single pulse of TCLK duration is generated to indicate that the device is idle and can be used again for programing any other timing interval. This device is non-retriggerable, meaning that other trigger pulses are ignored while the device is on duty.

A timer is a system that is used widely in industrial, manufacturing, telecommunications and aerospace applications. For instance, to name a few: staircase, irrigation, time lock, kitchen (egg timer), TV sleep function, watchdog, pulse generator, countdown, call timer, delay generator, timed switch or outlet, auto power off functions, energy saving systems, motor drivers and process sequencers, etc. Timers also become subsystems of many precision scientific instrumentation such as frequency meters or signal generators. Timers may be non-retriggerable or retriggerable, and may include a keypad to program timing period and 7-segment or LCD display to show current time count. Since the function of counting is very similar to timing, the programmable timer can be easily configured to operate as timer or as counter. This feature provides industry the ability to purchase and stock one device for use as a timer or counter. This double functionality will be studied in PIC18F microcontroller TMR0 in P12.

 

2. Planning

Planning several design phases (subprojects):

SP2_1

Due date April 5

Gate-level measurements (how fast is a circuit calculating?)

 

SP2_2

May 3

Analysing circuits based on 1-bit memory cells (FF)

 

 

SP2_3

May 10

Implementing finite state machines (FSM)

 

   

SP2_4

May 20

Implementing counters and data registers

 

P_Ch2

May 20 Report, video and project files Q & A

This chip can be designed internally using many strategies. To make it simple and reasonable in the given time constraints, and to be able to embed its design within CSD course timeline, we propose a given architecture represented in Fig. 3 based on the generalised dedicated processor architecture represented in Fig. 2.

We intent to adapt this circuit to microcontrollers in P_Ch3 empowering you to compare design features and product performance from both technologies: digital hardware based on FPGA and microcontrollers.

Generalised dedicated processor architecture

Fig. 2. General architecture of an advanced digital system or dedicated processor to solve a specific function or algorithm. Data inputs are information or signals to be processed by the device. In our project, the physical quantity to be processed is time; we intent to generate a pulse which time duration depends on pulse count (PC) and time base represented by the CLK signal. In our project, Chip3 is not used, and thus our information processor consist of Chip1 (control unit: FSM), and Chip2 (datapath or operation unit: registers, counters, memory cells, combinational circuits, etc.).

For this projects, it is assumed that CLK_Generator is not required, imagining the external OSC_CLK_in driving the FSM and the datapath, as represented in Fig. 3.

Dedicated processor

Fig. 3. Dedicated processor taylored for this application where the CLK_Geenrator is not used for simplicity.

planning

Fig. 4. Top level internal architecture for Prog_Timer. Datapath (Chip2) components allow counting CLK pulses and generating status signals for the control unit (Chip1).

Subprojects planning related to lab sessions:

1)  Lab4: SP2_1 is used to comprehend how to perform propagation delay measurements, gate-level simulations, timing analyser and circuit speed calculations. We will measure such parameters for the Comp_24bit (Chip2 in the Prog_timer datapath represented in Fig. 4).

2) Lab5: SP2_2 is used to discover how 1-bit memory cells work analysing a Circuit_type7493 based on flip-flops.

3) Lab6: SP2_3 is for implementing the system control unit Chip 1 as a canonical synchronous FSM. State diagram will be given as initial data because the project emphasis is placed on translating FSM into VHDL. A testbench schematic and its VHDL files will be supplied in order to test the control unit.

4) Lab7: SP2_4 is used to discuss how counters and registers are implemented in VHDL. Datapath's Chip1 and Chip3 will be given as initial resources and discussed in detail.

5) Complete Prog_timer using plan C2 and the components. 


Project location:

C:\CSD\P_Ch2\Prog_Timer\(files)


 

3. Developing

The development of P_Ch2 implies completing each subproject beforehand and the final construction in VHDL of the system Prog_timer in Fig. 3. Combine the Datapath from SP2_4 and the control unit from SP2_3 to implement the Prog_Timer.

Synthesise it and test the project using both functional and gate-level simulations triggering several times the device for different pulse count (PC) values.

NOTE: Solving these laboratory assignments requires studying ahead in group in detail similar examples and tutorials in CSD digsys. Ask questions on the projects to save study time and start working in the right direction. remember that solving this kind of semi-structured projects you will be able to solve similar exam problems.

 

4. Testing

Testing P_Ch2 implies testing SP2_2 and SP2_3 beforehand and the final verification of the circuit in Fig. 4 using several trigger signals and pulse count values.

Measure how fast is the circuit for a given target chip. Which is the shortest timing period (TP) that can be programmed?

Deduce the numbert of D_FF used in this design.



5. Reporting

Marking grid

Work assessments to be carried out in laboratory sessions:
  SP2_1 SP2_2 SP2_3  
  1p 1p 1p  

Note Work assesmment in lab sessions is Individual

 

P_Ch1 handwritten report and video presentation:
SP2_1 SP2_2 SP2_3 SP2_4 Video P_Ch2
1p 1p 1p 1p 1p 2p

Notes on lab assessment: student grades are not simply reflecting report or video quality, but implicitly, they include laboratory participation, questions and answers, problem solving skills, attendance and punctuality, active attitude and group work.

For instance, SP2_2 annex in PDF report may be a group submission including improvements on SP2_2 materials discussed during lab work assessments.

 


Follow this rubric for writing reports.


 

Some of your queries on reports and presentations are already answered at Q&A.