UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

SP1_2

Q&A

SP1_3: Circuit design using single-VHDL file plans A and B

SP1_4

Lab2
NOTE: This subproject must be solved only after having completed successfully lab session Lab2 because you will copy and adapt materials from it.

1. Specifications

The aim of this laboratory project is to invent a 2-bit adder (Adder_2bit) using EDA tools (synthesis and simulation) and putting into practice VHDL writing styles plan A (structural) and plan B (behavioural).

circuit

Fig. 1. Symbol of Adder_2bit circuit  and some truth table vectors.

 

NOTES on designing circuits:

- VHDL files are not assessed because what is of interest are schematics, flowcharts, sketches, diagrams, etc. that you prepare carefully using pen & paper with annotations and explanations all over project sections. In our introductory CSD course, VHDL files are required simply as straightforward translations of such schematics and flowcharts. Thus, do not write VHDL without a plan because is meaningless and do not mark.

- DO not change the name of the entity, other names are invalid. This circuit is named  Adder_2bit.

- Entity description (specifications) is always the same, whatever the plan you are intended to use as architecture.

- Be aware of what is a single wire such Cin, and what is a vector wire (cable) such S(1..0). Ports are represented in the circuit's symbol and described in the entity.

- Never copy and paste files or schematics from your colleagues; it has no meaning, it is like cheating, unfair, it is completely useless, no marks are given, you are not learning properly and thus, you likely fail exams.

- Never mix your project materials, but use the indicated folders in planning section below.

- Do not start trying to solve the Adder_2bit, but instead study, run and analyse how other tutorials examples are functioning. For instance, if you have interest in solving a circuit using flat behavioural method plan B, investigate firstly projects such Hex_7seg_decoder, Dec3_8, MUX_8, Adder_1bit, Comp_1bit, etc.

-Be aware that CSD lab projects are completely related to the whole course; when solving lab projects you learn the full subject and in this way you can as well get good marks in questionnaires and exams. If after solving such lab projects, you cannot solve similar exam assignments, something is not right; let us to know. 

- Do not invest too much time in a given question or design step, if there is something not clear enough, ask questions (this Q&A is where to find some answer to common questions). 

 

2. Planning

Entity description in the same for both plans.

Project location:

C:\CSD\P_Ch1\SP1_3\Adder_2bitA\

 Follow steps described in SP1_2 to obtain a synthesised circuit for a given target chip.

 

Project location:

C:\CSD\P_Ch1\SP1_3\Adder_2bitB\

Follow steps described in SP1_2 to obtain a synthesised circuit for a given target chip.

Develop plan A, and only when you finish it (1-2-3-4), start a new project for solving the same circuit using plan B (1-2-3-4 again).

3. Developing

Synthesis circuits for plan A and plan B. Target chip: MAX 10 10M50DAF484C7. Discuss the schematics, explain differences and similarities. How many chip resources (logic elements) are used? 

This exercise must be solved only after having completed lab session Lab2 comprehending how the MUX_8 is implemented using both plan A and B. Attending classes is necessary to save study time and collaborate with team mates. Questions that may be of interest will be posted at P_Ch1 Q&A page. 

 

4. Testing

Circuit verification using VHDL testbench fixture. Apply some stimulus translating input vectors from the initial timing diagram. Use time resolution referred to multiples of a Min_Pulse constant of 2.57 μs. 

Verify that both plans are working as expected using the same testbench file.

 

5. Reporting

Follow this rubric for writing reports. Because in this assignment you are solving two projects, at least eight sheets of paper are required.