upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Week 7

Week 8: Counters and registers

Week 9



[28/04, 04/05]

Guided activities #8

[P7]  Standard sequential circuits: synchronous counters as a FSM with state enumeration (Plan X)

Plan Y: Standard sequential circuits: synchronous counters as a FSM with STD_LOGIC_VECTOR signals and arithmetic libraries

 Standard sequential circuits: synchronous counters as a hierarchy of components (plan C2).

 

- Specifications: Symbol, inputs and outputs, output codes, timing diagram, function table, state diagram

Examine other comercial counters and new features:

- Counters type 74LS169, 74LS163, etc. counting code and features such as control inputs and outputs, reversibility, parallel load, expansion, etc.

- Counters for different binary codes: binary, Gray, one-hot, Johnson, etc.

- Plan: using a FSM enumerating all the states with labels

This is a BCD_Counter_mod100, an example of chaining (rippling) counters in Proteus (plan C2).


Let's develop and test the Counter_mod12 as a tutorial that yourself can follow. Comparison of alternative plans for designing counters.

- The Plan X (flat single-file project) as an enumerated FSM  like the Counter_BCD_1digit or the other examples in P6.

- The Plan Y (flat single-file project) as a FSM using the arithmetic library and STD_LOGIC_VECTOR signals.

- The Plan C2 (hierarchical multiple-file project) using the building block Counter_mod16. Count truncation, counter expandability.

 

The due date for the PLA#2.1 second Project PH is April 30--> May 3

 


[05/05, 11/05, 12/05]

Lecture #8

Additional standard sequential blocks: data and shift registers (Plan Y)

[P8] Dedicated processors (datapath + control unit + CLK generators)

CLK generator design. Frequency dividers.

 

Questionnaire #Q2.1 on P5 - P6, --> Delayed to May 12   

Other related projects for you to practise: Data register: the key component for saving data. Plan Y, which makes this device identical to the parallel load (LD) feature of the Counter_mod16. Shift register  (type 74LS194). Plan Y, where the parallel input - parallel output is also identical to the data register.

[P7] - [P8] Advanced project demonstration: Designing a digital timer.

Analysis of the Hour_Counter in P7.  Repeat and adapt the plan C2 based on truncating and chaining components Counter_mod16 to obtain a larger counter.

Run the HH:MM:SS example real-time clock available in Proteus and realise how many more counters can be organised in the same way applying the plan Z ideas on counter truncation and hiearchical design. 


Discussion of an advanced project: Designing the digital timer proposed in P8. The proposed architecture when the project is large and complex: the dedicated processor composed of:

- Datapath (registers and aritmetic and logic circuits)

- Control unit (FSM)

- CLK generator

- The CLK_Generator:  frequency dividers and the T_FF as a circuit to square pulsed signals.

- Oscillators. RC, quartz crystal, 555 chip, etc.  This is unit on CLK circuits based on gates or specific integrated circuits.


[08/05, 15/05]

Laboratory #8

[P7]  Examples of designing counters

Plan X:  Standard sequential circuits: synchronous counters as a FSM with state enumeration

Plan Y: Standard sequential circuits: synchronous counters as a FSM with STD_LOGIC_VECTOR signals and arithmetic libraries

 

-Plan X. State diagram, FSM architecture: 

--> Drawing of the state register, number of bits depending of the encoding (one-hot, binary sequential, Gray, etc.)

--> CC1, CC2 truth tables and their behavioural (flow chart) description (using labels for current_state and next_state signals).

Run a tutorial on how to build a 1-digit BCD counter using the state enumeration technique.

- Development: VHDL file

- Test bench to determine whether the counter works as expected.

This is an example of a 1-digit BCD counter that you can run in Proteus unzipping all the files in a folder like:

L:\CSD\P6\Counter_BCD_1digit\

 


-Plan Y. State diagram, FSM architecture,  use of the arithmetic library and STD_LOGIC_VECTOR signals (flat single-file project).

Run the tutorial on the Counter_mod16.

This is a key building block: the multifunctional/universal 16-bit binary counter: reversible, parallel load, rippling signals for count expansion, etc.

A synchronous (CLK) reversible (UD_L) expandable (CE and TC16) 4-bit binary counter type 74ALS169 with parallel (LD, D_in) inputs) to work as well as a data register.

Run the real prototype in a DE0 board from Digilent - Altera.

 

This is the due date for the PLA#2.2. (Project PI, May 15)