upc eetac_1

Week 6

Week 7: Finite state machines (FSM)

Week 8



[07/11]

Guided activities #7

 [P5 - P6] Implementing flip-flops as FSM

 

Resuming the course sequence. Go back to the previous week 6 and review the 1-bit memory cell concepts (latch, flip-flop, synchronous and asynchronous circuits, CLK. Here you'll find as well the design of the T_FF as a FSM based on D_FF in the state register.

 

Different methods to plan a flip-flop (D_FF, JK_FF, D_FF and T_FF):

  1. Using gates or equations (such it was the plan A in Chapter 1) . Not practical, only for study and theory purposes.

  2. Using other components (plan C2). For instance, invert a T_FF based on JK_FF, or invent a D_FF based on SR_FF. Not that practical, only for studying theory and fixing basic ideas.

  3. Based on a FSM architecture. Invent a JK_FF, T_FF or an RS_FF based on a FSM. This is the method to follow always for tiny sequential circuits. --> P6.

 

Let's discuss how to handle the PLA#2.1  in order to succeed.


[11/11]

Laboratory #7

[P6] Finite State Machines (FSM)

Example of a FSM. Classroom luminaires:

1 - 2 - 3 - 4: Specifications, planning, development and test

 

Let's study and run the tutorial on the control of the classroom luminaires using a single push-button. Specify and plan. In this way we'll be ready for solving a more complex FSM in the next sessions: a keyboard interface based on a matrix scanner.


Tutorial continuation. On the design of the classroom luminaries: Development and test. VHDL file following the FSM pattern, EDA tool project and synthesis, RTL circuit, testbench, functional simulation, gate-level simulation.

The next step after the VHDL testbenches: Download the project into a prototyping PLD board. Example of the 16-key matrix keyboard, the bike flashing torche, etc.

How to assign pins to the prototyping board? How to download the final PLD configuration file? Download the Light_Control into the prototyping board and experiment with the project. Why sometimes the circuit doesn't work or the pulses are not correctly sampled? (--> Invent a debouncing filter and use a suitable CLK frequency for the physical phenomena in study).   

 

This is the due date for the PLA#2.1.

 


[12/11]

Lecture #7

[P5] Method of ROM for solving logic functions

[P6] Examples of FSM design: a 16-key matrix encoder

 

The method of ROM to implement logic functions: the idea behind the lookup table (LUT) cell in FPGA.

 


Let's study and run the tutorial on the design of the 16-key matrix keyboard encoder specified in P6:  Specifications and plan: Commercial chip, keypad Proteus simulation, matrix circuit in rows and columns, state diagram, FSM, state register, CC1 and CC2 truth tables, CC1 and CC2 flowcharts.

 

On the design of the 16-key matrix keyboard encoder specified in P6:  Development and test. VHDL file following the FSM pattern, EDA tool project and synthesis, RTL circuit, testbench, functional simulation, gate-level simulation.