upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Week 5

Week 6: 1-bit memory cells: latches and flip-flops

Week 7


[31/03, 14/04]

Lecture #6

[P5] Theory on latches and flip-flops

How to design a latch using logic gates?

How to build a flip-flop using a latch as a component?


Questionnaire Q#1.2 on P3 and P4 (14/04, 08:01 - 08:28)

Let's continue with the RS latch internal structure derived from logic gates.

Let's present the different types of 1-bit memory cell: RS latch (asynchronous), and JK, D, T, and RS flip-flops (synchronous). This is the new building block that is going to be used along with combinational circuits form Chapter 1 to implement finite state machines (FSM). The symbols and function tables.

How to deduce an RS_FF from a RS latch? (RS_latch --> gated-RS latch --> RS flip-flop). Use these notes.

How to deduce a D_FF from the RS_FF? Use the same tutorial notes.

Finally so, fortunately, we'll describe the state register based on D_FF behaviourally in VHDL, which makes this circuit very simple and independent of the specific PLD technology.

Let's introduce the concept of finite state machine (FSM) as the standard synchronous sequential system to solve every application. For instance, simple FF or the keyboard encoder in P6.


Laboratory #6

[P5] Flip-flops. The CLK concept. Synchronicity and asynchronicity

T (toggle) flip-flop

Example of an asynchronous circuit


- The basic idea of an RS_latch cell (symbol, function table, timing diagram). Run in Proteus and in VHDL the RS latch example to comprehend how a 1-bit memory cell works. Develop and test the project based on NOR gates. Measure the propagation time (How long does ot take to save a '1' or a '0'?).

- The basic idea of an RS_FF (symbol, function table, timing diagram). Run in Proteus the RS_FFexample to see the difference now when the inputs are clocked.

- This is a data flip-flop D_FF described in VDHL using a plan B behavioural approach. Another valid way is to describe this D_FF as a FSM. 

- Les's simulate in Proteus and in VHDL an asynchronous sequential circuits based on synchronous flip-flops.

The point here is to see the drawbacks of such asynchronous design with respect to the synchronous design of finite state machines (FSM) that we'll discuss from the next sessions. Notes: (1). 

Run functional and gate-level simulations. To better observe how the circuit behave, decode the output of the asynchronous counter using a Dec_4_16 to obtain a 4-bit one-hot counter and observe the waveforms (Counter_0nehot_16bit_async). Detect false codes and glitches due to the circuit asynchronicity and propagation times.

More discussion of the drawbacks of asynchronous sequential circuits: Problems 5.8, 5.9. Comparison with this synchronous circuit in Problem 5.7. 


This is the due date for the PLA#1.1  and the PLA#1.2 



Guided activities #6

[P5] - [P6] FSM

Designing the T_FF and the JK_FF as a FSM


Let's use the D_FF as the state register (memory cell) of the FSM architecture. The FSM és the canonical synchronous sequential system.

As an example, Let's solve  a T_FF as a finite state machine (FSM), . Another timing diagram to remember how a T_FF works. Thus follow the tutorial.


Apply the same FSM method to complete the P5: the design of a JK_FF using the FSM methodology. After the development, focus your attention if translated the timing diagram sketch into a VHDL testbench to test functionally and at the gate-level the JK_FF. Measure how fast is the circuit.

And also practise about how to analyse an asynchronous circuit based on 1-bit memory cells.

And so, from now on, let's design FSM like the light control system of the classroom luminaires.