Week 5: Designing large combinational circuits 

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[P4] Radix2 and 2C numbers and circuits. Measurement of a circuit's operational speed Circuit propagation delay. Gatelevel simulation for circuit's propagation delay measurement 

Tutorials on gatelevel simulation. We'll use the 10bit binary adder required in the PLA#1.2 (Adder_10bit) for demonstrating both, how to translate a plan C2 schematic into VHDL, and how to measure the propagation delay of a circuit. Let's use for instance the Adder_8bit plan and VHDL file to copy and adapt them in this session.
Session outcomes: These are example files developed in the session: Entity Adder_10bit, Plan C2 for the Adder_10bit, and the VHDL file Adder_10bit.vhd, which has the components Adder_4bit.vhd and Adder_1bit.vhd the tutorials. This is a convenient testbench Adder_10bit_tb.vhd.
In the lab we have some commercial CPLD and FPGA target chips where to synthesise our circuits. For instance:
CPLD  FPGA  
Xilinx  XC2C256TQ144  7  Spartan3E XC3S500EFG320; 
IntelAltera  MAX II EPM2210F324C3  Cyclone III 3C16F484C6N 
Lattice  ispMach4128V TQFP100  MachXO 

Another opportunity to repeat delay measurements and circuit's speed calculations. The project Int_add_subt_8bit. Run a gatelevel simulation to measure its maximun speed of processing for a given target chip. All the necessary files for developing and testing this circuit.

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Lecture #5 
[P4] Other arithmetic circuits and Arithmetic and Logic Units (ALU) Planning circuits for maximising processing speed 

The general architecture of an arithmetic and logic unit (ALU): performing several operations in parallel and then selecting only one result. Example classic chip: 74LS181.
Other arithmetic circuits, along with the ones proposed in your PLA#1.2 (the design of a selectable_add_subt_comp_10bit) to allow further practice about the plan C2:
Play with a similar arithmetic circuit: the 8bit signed multiplier.
The circuit Int_comp_8bit has to include 3 outputs: GT (greater than) to detect when A > B, EQ (equal to) to detect when A = B, and LT (less than) to detect when A < B.
Let's discuss how to plan and implement the Int_add_subt_8bit. All the source VHDL files for this are stored in P4.

 The introductory ideas on propagation time in logic circuits, technology flat schematic for ta target chip and its postsynthesis model in VHDL (the VHO file)
This is the Project D in P3: A 4bit carrylookahead adder. The idea of a circuit's processing speed. Comparing internal design strategies: ripplecarry versus carry lookahead. All the necessary files are in this link.
Thus, to summarise this lesson, two kind of experiments are possible:
(1) A circuit synthesised for different PLD's. Different technologies or different vendors imply different speeds of processing.
(2) A circuit planned using different strategies synthesised in a given PLD. For instance, a ripplecarry and a carry lookahead adder will have different speeds of processing. Tutorial on the design of the Adder_4bit using carrylookahead techniques.
Other ideas
 Discuss the method of the plan C2 to implement larger circuits using simpler blocks hierarchically:
Examples of proposed arithmetic circuits: Adder_8bit  Int_add_subt_8bit, Comp_8bit  Int_comp_8bit, Mult_8bit  Int_mult_8bit, etc.
Examples of proposed logic blocks built on expanding circuits of the same kind (plan C2): Octuple_Mux_4 (Mux_2), Dec_4_16 (Dec_2_4), Enc_10_4 (Enc_4_2), etc.
 Discussion and Q & A on the Selectable _add_subt_comp_10bit for the PLA#1.2.

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Guided activities #5 
[P5] Chapter II: Sequential systems 1bit asynchronous memory cell: RS latch 

Let's start the Chapter 2 on sequential circuits discovering the RS latch that works like this.
This device allows writing and reading a bit of data, and thus implements the memory of a digital circuit, which is a fundamental concept.
How to build a RS latch from logic gates that you know from Chapter 1?