Week 4: Hierarchical design in VHDL and arithmetics in radix 2 

[09/03] 

[P3] New methods for designing logic functions: method of decoders (MoD) and method of multiplexers (MoM). Plan C2 

Since now, we've studied several ways to implement logic functions based on: canonical equations (maxterms or minterms), minimised equations (SoP or PoS), only NOR or onlyNAND transformations, or even any combination of equations. All of then related to a given circuit structure or plan A.
Now, we'll implement logic circuits using hierarchical structures (plan C2) based on the method of decoders (MoD) and the method of multiplexers (MoM).
Design the circuit_K using the method of decoders (complete solution). (MoD).
Design the circuit_C using the method of decoders (circuit, equation). (MoD)
Design the circuit_C using the method of multiplexers and a MUX_4 (idea). (MoM).
And there is another method left for the next P5: implementing circuit using RAM memory.

[10/03] 

Lecture #4 
[P3] Radix2 arithmetic circuits. Radix2 adders, comparators, multipliers [P4] Two's complement (2C) aritmetics for integer numbers 

Questionnaire Q#1.1 on P1  P2
Topics to be covered:
Binary numbers, symbols, range and how to perform additions.
Conversion from binary to decimal, decimal to binary, hexadecimal numbers.
How to use the simple calculator in programming mode to works with bin/hex/oct/dec numbers.

How to represent positive/negative numbers (integers): two's complement (2C) convention and range of values for a given number of N bits.
Operations with integers, overflow flag (OV): which is the algorithm to detect an overflow situation?
Play with the 8bit adder/subtractor available in Proteus. Addition: result R = A + B. Subtraction: result R = A  B = A + (B) = A + 2C(B) . The idea of a XOR gate of 2 inputs as a programmable (CNTL) inverter/buffer to be used as a 2C generator module.
There are other ways to implement substractors, like using a specific block Subtractor_1bit (see problem 3.10 in the CSD collection).
It is time for printing and reading the preparatory laboratory assignment PLA#1.2 for the next Lab #6

[13/03, 20/03] 

[P3] Training on plan C2 structural hierarchical design [P3] Arithmetic circuits: Adder_1bit, Adder_4bit, Adder_8bit 
online 
Plan C2 in the context of our VHDL design flow of combinational circuits. Let's describe hierarchical designs in VHDL using components and signals. Once you've learned how to do it, you can solve any large project in the same way.
Before attempting the Add_4bit or the Adder_8bit, study the following examples based on the plan C2:
Proposed topdown architecture <> VHDL files
 Try again the MUX_8 but now using smaller components of the same kind MUX_8, plan C2. This problem can also be considered as a MUX2 and MUX 4 expanding.
 Let's solve for instance the Project A in P3: An Adder_1bit based on the method of multiplexers (MoM) and using a MUX2 and a MUX4.
 Let's solve for instance the Project B in P3: An Adder_1bit based on the method of decoders (MoD)

 Let's solve the Project C in P3: the Adder_4bit (4bit ripplecarry adder).
 Let's solve the Project E in P3: The design of the Adder_8bit.
This is the due date for the PLA#1.1 (delayed to April 17)