Week 3: Designing standard (classic) combinational chips 

[30/09] 

[P2] Comparing implementations: flat (single VHDL file) design (structural/behavioural/hierarchical) Circuit MUX8  plan A: structural, plan B: behavioural HEX_7seg_decoder 

Tutorial on the design of the circuit MUX_8 (type 74HCT151) proposed in P2 where is completely explained:
Following the plan A) Flat structural VHDL. Using Minilog (tbl file) to get the SoP equation and then write it in VHDL. These are the files of interest: circuit and testbench to start.

Following the plan B). Flat behavioural VHDL. Copy and adapt source files and run the complete project. This time, you have up to 3 different files because we have infered 3 highlevel interpretations on the table (1). A circuit using the flow chart version (3) to be placed at: L:\CSD\P2\MUX_8B3\MUX_8.vhd
You can use the same testbench all the time.
This is a tutorial on a similar circuit: a dual 4channel multiplexer (Dual_MUX4) in case you need find ideas on how to copy and adapt VHDL files.
It is time for printing and reading the preparatory laboratory assignment PLA#1.1 for the next Lab #4 which is about designing combinational circuits using alternative plans A or B. In class time, we'll assign you individually a plan A or a plan B to solve the project.
Extra material to analyse in class or in your own study time:
1) Following the plan C1). Flat hierarchical VHDL. Find the schematic and VHDL file in our P2 page and run the complete project. [NOTE: This plan C1 is not recommended > because it is far better the plan C2 which uses several VHDL files to represent a hierarchical structure]
RECOMMENDED: Compare the RTL view of the 4 or 5 projects and discuss them. What about the technology views, the real circuits synthesised in the target chip?

[01/10] 

Lecture #3 
[P2] Standard combinational logic circuits: encoders and decoders. [P2] Design flow concept map for combinational circuits. Examples of application of the design flow 

Once we have understood the basic ideas on Boole's algebra and circuit analysis, and the basic standard combinational blocks were presented, let us start designing such circuits. We already have done it for the multiplexers such as the MUX_8. This is the framework: concept map and the VHDL design flow that we'll go repeating once and again for every chip and design plan.
Planning alternative ways for designing their internal architecture:
Plan A) Structural (flat)  One VHDL file using equations
Plan B) Behavioural (flat)  One VHDL file using the truth table or algorithm
Plan C1) Structural (hierarchical)  One VHDL using equations (complicated/not recommended)
Plan C2) Structural (hierarchical)  several VHDL files using equations COMPONENTS and SIGNALS. This is the best design approach and so, from P3 and on all the projects will be organised in this fashion.
let's do the same for decoders, encoders, etc.), other standard combinational circuits that can be completely implemented following a given plan A, B, or C2.
Decoders. (1) Symbol, (2) truth table or equations, (3) timing diagram, (4) commercial chip, (5) internal design (Plan A, B, C1 or C2), (6) how to expand them (Plan C2)?
 Plan A. Dec_3_8 decoder using equations.
 Plan B. Dec_3_8 decoder. Follow the tutorial and examine the different truth table high level interpretations.
And the same for encoders (and also later for arithmetic circuits).

Yet another example, the Hex_7seg_decoder. It is a circuit to drive the typical 7segment displays. Run the circuit in Proteus to figure out how it works.
 Plan A. HEX to 7 SEG decoder (type 74LS47). Using a structural approach based on minimised equations (SoP / PoS).
 Plan B. HEX to 7 SEG decoder (type 74LS47). Using a behavioural (highlevel) description (truth table or algorithm) approach.
And finally:
 How to drive a 7segment commonanode or commoncathode display?
 How to calculate the limiting resistor? You can run this Circuit in Proteus to get an idea on voltage levels, currents, power consumption and logic values. Read more about electrical characteristics.(VOHmin, VOLmax, etc.)

[03/10] 

Guided activities #3 
[P2] Examples of incomplete logic functions [P3] Plan C2. Designing logic functions using the method of decoders (MoD) or the method of multiplexers (MoM). 

An example of incomplete function where the truth table is not completelly specified.
Implementing logic circuits using hierarchical structures (Plan C2) based on the method of decoders (MoD) and the method of multiplexers (MoM)
Design the circuit_K using the method of decoders (complete solution). (MoD).
Design the circuit_C using the method of decoders (circuit, equation). (MoD)
Design the circuit_C using the method of multiplexers and a MUX_4 (idea). (MoM).
Additional concepts and tutorials to study and practise
As an EETAC  UPC student, you can borrow books or download their electronic versions on the subject. We hugely recommend reading books on the subject to complement your class notes and get a broader view of the whole area of digital electronics.

Hint: study and solve the projects to the end. Print & write the corresponding 4sheetofpaper report for each project adding theory and whatever else you find useful in order to have good materials and class notes to study the subject. Simulate the testbench to certify that your design is correct. Annotate your questions and find answers in office time or at the next class. Remember that we are assuming that up to now: 3 weeks of classes > 15 hours of tuition in class and 15 hours out of class of your study time.