Week 2: Analysis and design concepts 

[19/09] 

Guided activities #2 
[P1 Section B]. Designing combinational circuits. Minimisation of logic functions. PoS and SoP. Minilog 

Design flow (P1section B). Draw the circuits corresponding to canonical equations based on maxterns or minterms.
 For example, this is a solution of the Circuit _W (named Circuit_3B) using the canonical expression sum of minterms.
Related to the Boolean analysis of circuit equations are the concepts of PoS and SoP, as represented in the P1 Section A  method #3. These important concepts are necessary as well in the P1 section B to design the Circuit_1 and the Circuit_2 as represented in the plan.
There is a software that we use to automatically minimise equations: minilog.exe or Logic Friday. Let's run a tutorial demonstration on how the minimiser works to obtain simplified equations from an initial truth table. The interpretation of the output table format will produce the SoP or PoS expressions and their corresponding logic circuits. For this tutorial, you can choose either (1) the circuit here or (2) the circuit here.
This is the plan or procedure to obtain results and complete the project:
1. Project location: L:\CSD\P1\minilog\
2. Find and modify a similar tbl file (for example from here)
3. Run Minilog and simplify using single output mode (SoM), table output format and choose between SoP or PoS. Remember that the SoP solution is a project (a circuit), and the PoS solution is another project (another circuit) that has to be reported in different sheets.
4. Table format interpretation so that you get the SoP or PoS equations. Be aware that in Minilog doesn't matter if you are working with zeros or ones: a '1' in the output table format always means the input variable and a '0' always means the input variable inverted (not).
5. Draw the circuits. Check the equation using WolframAlpha or the circuit using Proteus. This is verifying that the circuit that you have designed has the same given initial truth table.
 For example, this is an example solution of the Circuit_1 built using SoP (files).
Once this tutorial finished, try other examples from the Circuit_C, Circuit_K, etc. truth tables.

[23/09] 

[P1] Introduction to VHDL. Circuit synthesis and simulation using VHDL EDA tools Circuit synthesis. RTL view Circuit functional simulation. VHDL test bench 

Before advancing towards the P2 on the design of standard combinational circuits using VHDL tools, let's discover how to solve the last P1 Section A  method 4 using the VHDL language and electronic design automation (EDA) tools to synthesise and simulate a circuit with the aim of deducing its truth table.
1. Specifications: Find the truth table of the Circuit_W (or the Circuit_C or the Circuit_K) using VHDL synthesis and simulation tools. Draw an example of timing diagram.
2. The plan: Some notes (1). This below is a step by step to follow the tutorial.
3. Let's develop and synthesise (in Quartus II or in Xilinx ISE or in ispLEVER Classic)
A. Find the circuit's equation and write the VHDL source file from a similar file in digsys (P2). This is a VHDL source file example Circuit_W.vhd.
B. Start a new project using commercial PLD vendor tools. We choose a different toolset every semester. Here you are different devices available in our labs for experimentation. Select a target PLD chip (FPGA or CPLD) where the logic functions will be downloaded:






C. Run the synthesis process and examine the RTL view and the technology view. Print the circuit using the snipping tool. Annotate and comment the differences. Discuss the similarities with respect our initial circuit. Start a new project using a target chip from a different family and inspect both, the RTL and the technology schematics.

4. Let's test and verify (in ModelSim Altera or in Xilinx ISim or in ActiveHDL).
D. Generate a testbench template in Quartus II (or in ISim or in ActiveHDL). This is the idea (Visio) behind a VHDL testbench. If necessary, depending on the EDA tool, rename the file from Circuit_W.vht to Circuit_W_tb.vhd and copy it to the project location folder. Using an example timing diagram, add the stimulus inputs and the constant Min_Pulse. This is a VHDL testbench example Circuit_W_tb.vhd which can be copied and adapted. Some notes (2).
E. Start a project in ModelSim Altera (or in Xilinx ISim or in ActiveHDL). Run the simulation process and extract the truth table from the inspection of the logic analyser display.





F. Compare the truth table with the one obtained using other methods to check the development results. Print the waveforms of the timing diagram, add comments and deduce the truth table that has to coincide with the one deduced using other methods.
Now, run again the complete process for other example circuits. This is an example of a complete tutorial for the Circuit_K.

[26/09] 

Lecture #2 
[P1] Design concept: Multiple circuits that satisfy the specifications (truth table): Canonical, SoP, PoS, only NOR, only NAND, etc. [P2] Standard combinational logic circuits: multiplexers, demultiplexers 

Now that you know how to use the minimiser minilog, what is left to finish P1 Section B is to discuss how to build circuits from the same truth table using onlyNAND or only NOR gates.
 Circuits using onlyNOR (Circuit_5) or using onlyNAND (Circuit_4) can be solved studying these notes. Just try it.
This is your time for summarising P1 and solving other example problems from the collection.

Standard common logic circuits: The concepts related to the specifications and theory on any simple circuit.
For example:
Multiplexers. (1) Symbol, (2) truth table or equations, (3) timing diagram, (4) commercial chip, (5) internal design (Plan A, B, C1 or C2), (6) how to expand them (Plan C2)?
And the same for demultiplexers. Which is the symbol and circuit's truth table of a Demux_16?
Additional concepts and tutorials to study and practise
In the same way and using VHDL tools you can obtain the truth table of the Circuit_C and the Circuit_K (which is solved as an example here).