﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC
 Bachelor's Degree in Telecommunications Systems and in Network Engineering

PLA3

Q&A

## PLA4: Gate-level and timing analyser measurements

PLA5

 NOTE: This post lab assignment must be solved only after having completed successfully lab session because you will copy and adapt materials from it.

General ideas on this PLA are presented in this picture. Our main goal is you to learn the course content and concepts up to P4 regarding combinational circuits analysis and design. Ask questions if you have douts. In this Q&A section you wil find some common questions and answers.

 Fig. 1. Concepts, ideas and planning the PLA4. If you find it necessary, learn about measurements and how to run the new tools in a simpler circuit firstly, like an Adder_1bit, Comp_1bit or MUX_4.

We will continue the project Comp_16bit proposed in PLA3 characterising how fast is the circuit for a given target chip and internal architecture. This PLA is adapted from problem .

- Calculate the propagation delay in a given signal transition using gate-level simulations.

- Calculate the circuit's longest propagation delay and maximum speed for a given target chip.

- Demonstrate that the circuit does not calculate correctly when Min_Pulse is shorter that the circuit's propagation delay.

 Fig. 1. Comp_16bit symbol.

Project location: C:\CSD\P4\PLA4\Comp_16bit\(files)

Specifications (signed integer Int_Comp_16bit)

We will continue the project Int_Comp_16bit proposed in PLA3 characterising how fast is the circuit for a given target chip and internal architecture. This PLA is adapted from problem .

- Calculate the propagation delay in a given signal transition using gate-level simulations.

- Calculate the circuit's longest propagation delay and maximum speed for a given target chip.

- Demonstrate that the circuit does not calculate correctly when Min_Pulse is shorter that the circuit's propagation delay.

 Fig. 1. Symbol.

Project location: C:\CSD\P4\PLA4\Int_Comp_16bit\(files)

 Example of individual assignments (your instructor will indicate you which during lab session) Circuit Comp_1bit plan Target chip Test vectors Est. 1 Comp_16bit A Cyclone IV ··· Est. 2 Int_Comp_16bit C2 MoD MAX II ··· Est. 3 Comp_16bit B Cyclone IV 3541, 40387, 202, 33914, 65534, 18 Est. 4 Int_Comp_16bit C2 MoD Cyclone IV -32766, -14600, -12, +18, +27433, +12368 Est. 5 Comp_16bit C2 MoM MAX II ··· ··· ··· ··· ··· ···