ispLEVER Classic 2.1.00.02.49.20 Fitter Report File

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Project Name : counter_bcd_1digit_top_prj Project Path : C:\CSD\JK_HWD\Counter_BCD_mod60_top Device : M4128_64 Package : 100 GLB Input Mux Size : 19 Available Blocks : 8 Speed : -7.5 Part Number : LC4128V-75T100I Source Format : Pure_VHDL Project 'counter_bcd_1digit_top_prj' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.01 secs Partition Time 0.03 secs Place Time 0.00 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 8 Total Logic Functions 54 Total Output Pins 24 Total Bidir I/O Pins 0 Total Buried Nodes 30 Total Flip-Flops 38 Total D Flip-Flops 23 Total T Flip-Flops 15 Total Latches 0 Total Product Terms 298 Total Reserved Pins 0 Total Locked Pins 32 Total Locked Nodes 0 Total Unique Output Enables 0 Total Unique Clocks 3 Total Unique Clock Enables 2 Total Unique Resets 1 Total Unique Presets 1 Fmax Logic Levels 1 Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 1 3 --> 25 Input-Only Pins 6 0 6 --> 0 I/O / Enable Pins 2 1 1 --> 50 I/O Pins 62 30 32 --> 48 Logic Functions 128 54 74 --> 42 Input Registers 64 0 64 --> 0 GLB Inputs 288 155 133 --> 53 Logical Product Terms 640 217 423 --> 33 Occupied GLBs 8 8 0 --> 100 Macrocells 128 54 74 --> 42 Control Product Terms: GLB Clock/Clock Enables 8 5 3 --> 62 GLB Reset/Presets 8 0 8 --> 0 Macrocell Clocks 128 0 128 --> 0 Macrocell Clock Enables 128 3 125 --> 2 Macrocell Enables 128 0 128 --> 0 Macrocell Resets 128 0 128 --> 0 Macrocell Presets 128 0 128 --> 0 Global Routing Pool 220 46 174 --> 20 GRP from IFB .. 7 .. --> .. (from input signals) .. 7 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 39 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 0 14 14 0/8 0 5 0 11 26 7 GLB B 0 22 22 0/8 0 7 1 8 36 10 GLB C 6 21 27 4/8 0 10 0 6 29 10 GLB D 2 20 22 3/8 0 6 0 10 26 8 ------------------------------------------------------------------------------------------- GLB E 8 14 22 0/8 0 2 0 14 13 3 GLB F 0 12 12 8/8 0 8 0 8 33 9 GLB G 22 4 26 8/8 0 8 0 8 26 8 GLB H 6 4 10 7/8 0 8 0 8 28 8 ------------------------------------------------------------------------------------------- TOTALS: 44 111 155 30/64 0 54 1 73 217 63 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 0 0 0 0 0 0 0 GLB B 1 0 0 2 0 0 0 GLB C 1 0 0 0 0 0 0 GLB D 1 0 0 1 0 0 0 ------------------------------------------------------------------------------ GLB E 1 0 0 0 0 0 0 GLB F 1 0 0 0 0 0 0 GLB G 0 0 0 0 0 0 0 GLB H 0 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name -------------------------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 | I_O | 0 |B0 | | | | 4 | I_O | 0 |B2 | | | | 5 | I_O | 0 |B4 | | | | 6 | I_O | 0 |B6 | | | | 7 |GNDIO0 | - | | | | | 8 | I_O | 0 |B8 | | | | 9 | I_O | 0 |B10 | | | | 10 | I_O | 0 |B12 | | | | 11 | I_O | 0 |B13 | | | | 12 | IN0 | 0 | | | | | 13 |VCCIO0 | - | | | | | 14 | I_O | 0 |C14 | * |LVCMOS18 | Input |CD_L 15 | I_O | 0 |C12 | | | | 16 | I_O | 0 |C10 | * |LVCMOS18 | Input |CPB_L 17 | I_O | 0 |C8 | | | | 18 |GNDIO0 | - | | | | | 19 | I_O | 0 |C6 | * |LVCMOS18 | Input |Sel_filter 20 | I_O | 0 |C5 | | | | 21 | I_O | 0 |C4 | * |LVCMOS18 | Input |Sel_pulse 22 | I_O | 0 |C2 | | | | 23 | IN1 | 0 | | | | | 24 | TCK | - | | | | | 25 | VCC | - | | | | | 26 | GND | - | | | | | 27 | IN2 | 0 | | | | | 28 | I_O | 0 |D13 | * |LVCMOS18 | Input |Sel_CLK_freq 29 | I_O | 0 |D12 | | | | 30 | I_O | 0 |D10 | * |LVCMOS18 | Input |UD_L 31 | I_O | 0 |D8 | * |LVCMOS18 | Input |CE 32 |GNDIO0 | - | | | | | 33 |VCCIO0 | - | | | | | 34 | I_O | 0 |D6 | | | | 35 | I_O | 0 |D4 | | | | 36 | I_O | 0 |D2 | | | | 37 | I_O | 0 |D0 | | | | 38 |INCLK1 | 0 | | | | | 39 |INCLK2 | 1 | | | | | 40 | VCC | - | | | | | 41 | I_O | 1 |E0 | | | | 42 | I_O | 1 |E2 | | | | 43 | I_O | 1 |E4 | | | | 44 | I_O | 1 |E6 | | | | 45 |VCCIO1 | - | | | | | 46 |GNDIO1 | - | | | | | 47 | I_O | 1 |E8 | | | | 48 | I_O | 1 |E10 | | | | 49 | I_O | 1 |E12 | | | | 50 | I_O | 1 |E14 | | | | 51 | GND | - | | | | | 52 | TMS | - | | | | | 53 | I_O | 1 |F0 | * |LVCMOS18 | Output|LU_0_ 54 | I_O | 1 |F2 | * |LVCMOS18 | Output|LU_1_ 55 | I_O | 1 |F4 | * |LVCMOS18 | Output|LU_2_ 56 | I_O | 1 |F6 | * |LVCMOS18 | Output|LU_3_ 57 |GNDIO1 | - | | | | | 58 | I_O | 1 |F8 | * |LVCMOS18 | Output|LT_0_ 59 | I_O | 1 |F10 | * |LVCMOS18 | Output|LT_1_ 60 | I_O | 1 |F12 | * |LVCMOS18 | Output|LT_2_ 61 | I_O | 1 |F13 | * |LVCMOS18 | Output|LT_3_ 62 | IN3 | 1 | | | | | 63 |VCCIO1 | - | | | | | 64 | I_O | 1 |G14 | * |LVCMOS18 | Output|LED_CLK_1Hz_SQ 65 | I_O | 1 |G12 | * |LVCMOS18 | Output|Ub 66 | I_O | 1 |G10 | * |LVCMOS18 | Output|Uc 67 | I_O | 1 |G8 | * |LVCMOS18 | Output|Ua 68 |GNDIO1 | - | | | | | 69 | I_O | 1 |G6 | * |LVCMOS18 | Output|Uf 70 | I_O | 1 |G5 | * |LVCMOS18 | Output|Ud 71 | I_O | 1 |G4 | * |LVCMOS18 | Output|Ug 72 | I_O | 1 |G2 | * |LVCMOS18 | Output|Ue 73 | IN4 | 1 | | | | | 74 | TDO | - | | | | | 75 | VCC | - | | | | | 76 | GND | - | | | | | 77 | IN5 | 1 | | | | | 78 | I_O | 1 |H13 | * |LVCMOS18 | Output|TC60 79 | I_O | 1 |H12 | * |LVCMOS18 | Output|Tb 80 | I_O | 1 |H10 | * |LVCMOS18 | Output|Tc 81 | I_O | 1 |H8 | * |LVCMOS18 | Output|Ta 82 |GNDIO1 | - | | | | | 83 |VCCIO1 | - | | | | | 84 | I_O | 1 |H6 | * |LVCMOS18 | Output|Tf 85 | I_O | 1 |H4 | * |LVCMOS18 | Output|Td 86 | I_O | 1 |H2 | * |LVCMOS18 | Output|Tg 87 | I_O/OE| 1 |H0 | * |LVCMOS18 | Output|Te 88 |INCLK3 | 1 | | | | | 89 |INCLK0 | 0 | | * |LVCMOS18 | Input |OSC_CLK_in 90 | VCC | - | | | | | 91 | I_O/OE| 0 |A0 | | | | 92 | I_O | 0 |A2 | | | | 93 | I_O | 0 |A4 | | | | 94 | I_O | 0 |A6 | | | | 95 |VCCIO0 | - | | | | | 96 |GNDIO0 | - | | | | | 97 | I_O | 0 |A8 | | | | 98 | I_O | 0 |A10 | | | | 99 | I_O | 0 |A12 | | | | 100 | I_O | 0 |A14 | | | | -------------------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ----------------------------------------------- 14 C I/O 7 ABCDEFG- Up CD_L 31 D I/O 2 -----F-H Up CE 16 C I/O 1 --C----- Up CPB_L 89 -- INCLK -------- Up OSC_CLK_in 28 D I/O 1 --C----- Up Sel_CLK_freq 19 C I/O 1 --C----- Up Sel_filter 21 C I/O 1 --C----- Up Sel_pulse 30 D I/O 2 -----F-H Up UD_L ----------------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- 64 G 22 1 1 1 TFF * R 1 --C----- Fast Up LED_CLK_1Hz_SQ 58 F 12 1 4 1 TFF * R 2 -----F-H Fast Up LT_0_ 59 F 12 1 7 2 TFF * R 2 -----F-H Fast Up LT_1_ 60 F 12 1 5 1 TFF * R 2 -----F-H Fast Up LT_2_ 61 F 12 1 3 1 TFF * R 2 -----F-H Fast Up LT_3_ 53 F 8 1 3 1 DFF * R 3 -----FGH Fast Up LU_0_ 54 F 8 1 5 1 TFF * R 3 -----FGH Fast Up LU_1_ 55 F 8 1 3 1 TFF * R 3 -----FGH Fast Up LU_2_ 56 F 8 1 3 1 TFF * R 3 -----FGH Fast Up LU_3_ 78 H 10 1 3 1 COM -------- Fast Up TC60 81 H 4 - 4 1 COM -------- Fast Up Ta 79 H 4 - 4 1 COM -------- Fast Up Tb 80 H 4 - 3 1 COM -------- Fast Up Tc 85 H 4 - 4 1 COM -------- Fast Up Td 87 H 4 - 3 1 COM -------- Fast Up Te 84 H 4 - 4 1 COM -------- Fast Up Tf 86 H 4 - 3 1 COM -------- Fast Up Tg 67 G 4 - 4 1 COM -------- Fast Up Ua 65 G 4 - 4 1 COM -------- Fast Up Ub 66 G 4 - 3 1 COM -------- Fast Up Uc 70 G 4 - 4 1 COM -------- Fast Up Ud 72 G 4 - 3 1 COM -------- Fast Up Ue 69 G 4 - 4 1 COM -------- Fast Up Uf 71 G 4 - 3 1 COM -------- Fast Up Ug ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ----------------------------------------------------------------------- ----------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ------------------------------------------------------------------------------ 5 A 12 1 5 1 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_0_ 6 C 13 1 2 1 TFF * R 6 ABCDE-G- Chip2_Chip1_present_state_10_ 7 A 14 1 2 1 TFF * R 6 ABCDE-G- Chip2_Chip1_present_state_11_ 5 B 14 1 7 2 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_12_ 3 B 13 1 8 2 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_1_ 3 E 14 1 9 2 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_2_ 3 C 11 1 7 2 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_3_ 3 D 12 1 8 2 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_4_ 1 A 13 1 9 2 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_5_ 1 B 14 1 10 2 DFF * R 6 ABCDE-G- Chip2_Chip1_present_state_6_ 1 C 14 1 9 2 TFF * R 6 ABCDE-G- Chip2_Chip1_present_state_7_ 1 D 14 1 9 2 TFF * R 6 ABCDE-G- Chip2_Chip1_present_state_8_ 3 A 14 1 9 2 TFF * R 6 ABCDE-G- Chip2_Chip1_present_state_9_ 11 A 14 1 1 1 TFF * R 1 --C----- Chip2_Chip2_current_state_0_ 9 B 16 1 2 1 DFF * R * 4 -B-DE-G- Chip2_Chip3_present_state_0_ 5 D 17 1 3 1 DFF * R * 4 -B-DE-G- Chip2_Chip3_present_state_1_ 12 B 17 1 2 1 DFF * R * 4 -B-DE-G- Chip2_Chip3_present_state_2_ 12 D 17 1 1 1 TFF * R 1 --C----- Chip2_Chip4_current_state_0_ 9 D 21 1 2 1 DFF * R * 4 -B-DE-G- Chip2_Chip5_present_state_0_ 0 B 22 1 4 1 DFF * R * 4 -B-DE-G- Chip2_Chip5_present_state_1_ 7 D 21 1 3 1 DFF * R * 4 -B-DE-G- Chip2_Chip5_present_state_2_ 9 E 22 1 4 1 DFF * R * 4 -B-DE-G- Chip2_Chip5_present_state_3_ 7 B 22 1 3 1 DFF * R * 4 -B-DE-G- Chip2_Chip5_present_state_4_ 4 C 5 1 1 1 DFF * S 1 --C----- Chip5_current_state_0_ 7 C 4 1 1 1 DFF * R 1 --C----- Chip5_current_state_1_ 9 C 4 1 1 1 DFF * R 1 --C----- Chip5_current_state_2_ 2 C 4 1 1 1 DFF * R 1 --C----- Chip5_current_state_3_ 5 C 7 1 2 1 DFF * R 1 --C----- Chip5_current_state_4_ 12 C 4 1 1 1 DFF * R 1 --C----- Chip5_current_state_5_ 0 C 9 - 4 1 COM 1 -----F-- N_9_i ------------------------------------------------------------------------------ <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
Chip2_Chip1_present_state_0_.D = !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_0_.Q # !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_0_.Q & !Chip2_Chip1_present_state_9_.Q # !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_0_.Q & !Chip2_Chip1_present_state_8_.Q # !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_0_.Q & !Chip2_Chip1_present_state_7_.Q # !Chip2_Chip1_present_state_0_.Q & !Chip2_Chip1_present_state_12_.Q ; (5 pterms, 11 signals) Chip2_Chip1_present_state_0_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_0_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_10_.T = Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & !Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_12_.Q ; (2 pterms, 12 signals) Chip2_Chip1_present_state_10_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_10_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_11_.T = Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & !Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_12_.Q ; (2 pterms, 13 signals) Chip2_Chip1_present_state_11_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_11_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_12_.D = Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & !Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & !Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_12_.Q ; (7 pterms, 13 signals) Chip2_Chip1_present_state_12_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_12_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_1_.D = !( Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_0_.Q & !Chip2_Chip1_present_state_1_.Q # Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_12_.Q ) ; (8 pterms, 12 signals) Chip2_Chip1_present_state_1_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_1_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_2_.D = !( Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q # Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_1_.Q & !Chip2_Chip1_present_state_2_.Q # !Chip2_Chip1_present_state_0_.Q & !Chip2_Chip1_present_state_2_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_12_.Q ) ; (9 pterms, 13 signals) Chip2_Chip1_present_state_2_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_2_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_3_.D = !( Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q # Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_2_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_1_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_0_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_12_.Q ) ; (7 pterms, 10 signals) Chip2_Chip1_present_state_3_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_3_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_4_.D = !( Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q # Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_2_.Q # !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_1_.Q # !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_0_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_12_.Q ) ; (8 pterms, 11 signals) Chip2_Chip1_present_state_4_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_4_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_5_.D = !( Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q # Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_2_.Q # !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_1_.Q # !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_0_.Q # !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_5_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_12_.Q ) ; (9 pterms, 12 signals) Chip2_Chip1_present_state_5_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_5_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_6_.D = !( Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q # Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_2_.Q # !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_1_.Q # !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_0_.Q # !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q # !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_6_.Q # !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_6_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_12_.Q ) ; (10 pterms, 13 signals) Chip2_Chip1_present_state_6_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_6_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_7_.T = Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & !Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_12_.Q ; (9 pterms, 13 signals) Chip2_Chip1_present_state_7_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_7_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_8_.T = Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & !Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_12_.Q ; (9 pterms, 13 signals) Chip2_Chip1_present_state_8_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_8_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip1_present_state_9_.T = Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & !Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_6_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_5_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_4_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_3_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q # Chip2_Chip1_present_state_10_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (9 pterms, 13 signals) Chip2_Chip1_present_state_9_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip1_present_state_9_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip2_current_state_0_.T = !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 13 signals) Chip2_Chip2_current_state_0_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip2_current_state_0_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip3_present_state_0_.D = !Chip2_Chip3_present_state_0_.Q & !Chip2_Chip3_present_state_2_.Q ; (1 pterm, 2 signals) Chip2_Chip3_present_state_0_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip3_present_state_0_.CE = !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 13 signals) Chip2_Chip3_present_state_0_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip3_present_state_1_.D = Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & !Chip2_Chip3_present_state_2_.Q # !Chip2_Chip3_present_state_1_.Q & Chip2_Chip3_present_state_0_.Q & !Chip2_Chip3_present_state_2_.Q ; (2 pterms, 3 signals) Chip2_Chip3_present_state_1_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip3_present_state_1_.CE = !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 13 signals) Chip2_Chip3_present_state_1_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip3_present_state_2_.D = Chip2_Chip3_present_state_1_.Q & Chip2_Chip3_present_state_0_.Q & !Chip2_Chip3_present_state_2_.Q ; (1 pterm, 3 signals) Chip2_Chip3_present_state_2_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip3_present_state_2_.CE = !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 13 signals) Chip2_Chip3_present_state_2_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip4_current_state_0_.T = !Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & Chip2_Chip3_present_state_2_.Q & !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 16 signals) Chip2_Chip4_current_state_0_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip4_current_state_0_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip5_present_state_0_.D = !Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_3_.Q & !Chip2_Chip5_present_state_0_.Q # !Chip2_Chip5_present_state_0_.Q & !Chip2_Chip5_present_state_4_.Q ; (2 pterms, 4 signals) Chip2_Chip5_present_state_0_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip5_present_state_0_.CE = !Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & Chip2_Chip3_present_state_2_.Q & !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 16 signals) Chip2_Chip5_present_state_0_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip5_present_state_1_.D = !Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_3_.Q & Chip2_Chip5_present_state_0_.Q & !Chip2_Chip5_present_state_1_.Q # !Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_3_.Q & !Chip2_Chip5_present_state_0_.Q & Chip2_Chip5_present_state_1_.Q # Chip2_Chip5_present_state_0_.Q & !Chip2_Chip5_present_state_1_.Q & !Chip2_Chip5_present_state_4_.Q # !Chip2_Chip5_present_state_0_.Q & Chip2_Chip5_present_state_1_.Q & !Chip2_Chip5_present_state_4_.Q ; (4 pterms, 5 signals) Chip2_Chip5_present_state_1_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip5_present_state_1_.CE = !Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & Chip2_Chip3_present_state_2_.Q & !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 16 signals) Chip2_Chip5_present_state_1_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip5_present_state_2_.D = !Chip2_Chip5_present_state_2_.Q & Chip2_Chip5_present_state_0_.Q & Chip2_Chip5_present_state_1_.Q & !Chip2_Chip5_present_state_4_.Q # Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_1_.Q & !Chip2_Chip5_present_state_4_.Q # Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_0_.Q & !Chip2_Chip5_present_state_4_.Q ; (3 pterms, 4 signals) Chip2_Chip5_present_state_2_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip5_present_state_2_.CE = !Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & Chip2_Chip3_present_state_2_.Q & !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 16 signals) Chip2_Chip5_present_state_2_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip5_present_state_3_.D = Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_3_.Q & Chip2_Chip5_present_state_0_.Q & Chip2_Chip5_present_state_1_.Q & !Chip2_Chip5_present_state_4_.Q # Chip2_Chip5_present_state_3_.Q & !Chip2_Chip5_present_state_1_.Q & !Chip2_Chip5_present_state_4_.Q # Chip2_Chip5_present_state_3_.Q & !Chip2_Chip5_present_state_0_.Q & !Chip2_Chip5_present_state_4_.Q # !Chip2_Chip5_present_state_2_.Q & Chip2_Chip5_present_state_3_.Q & !Chip2_Chip5_present_state_4_.Q ; (4 pterms, 5 signals) Chip2_Chip5_present_state_3_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip5_present_state_3_.CE = !Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & Chip2_Chip3_present_state_2_.Q & !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 16 signals) Chip2_Chip5_present_state_3_.AR = !CD_L ; (1 pterm, 1 signal) Chip2_Chip5_present_state_4_.D = Chip2_Chip5_present_state_2_.Q & Chip2_Chip5_present_state_3_.Q & Chip2_Chip5_present_state_0_.Q & Chip2_Chip5_present_state_1_.Q & !Chip2_Chip5_present_state_4_.Q # !Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_3_.Q & !Chip2_Chip5_present_state_1_.Q & Chip2_Chip5_present_state_4_.Q # !Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_3_.Q & !Chip2_Chip5_present_state_0_.Q & Chip2_Chip5_present_state_4_.Q ; (3 pterms, 5 signals) Chip2_Chip5_present_state_4_.C = OSC_CLK_in ; (1 pterm, 1 signal) Chip2_Chip5_present_state_4_.CE = !Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & Chip2_Chip3_present_state_2_.Q & !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 16 signals) Chip2_Chip5_present_state_4_.AR = !CD_L ; (1 pterm, 1 signal) Chip5_current_state_0_.D = CPB_L & !Chip5_current_state_3_.Q & !Chip5_current_state_4_.Q ; (1 pterm, 3 signals) Chip5_current_state_0_.C = Chip2_Chip2_current_state_0_.Q ; (1 pterm, 1 signal) Chip5_current_state_0_.AP = !CD_L ; (1 pterm, 1 signal) Chip5_current_state_1_.D = !CPB_L & Chip5_current_state_0_.Q ; (1 pterm, 2 signals) Chip5_current_state_1_.C = Chip2_Chip2_current_state_0_.Q ; (1 pterm, 1 signal) Chip5_current_state_1_.AR = !CD_L ; (1 pterm, 1 signal) Chip5_current_state_2_.D = !CPB_L & Chip5_current_state_1_.Q ; (1 pterm, 2 signals) Chip5_current_state_2_.C = Chip2_Chip2_current_state_0_.Q ; (1 pterm, 1 signal) Chip5_current_state_2_.AR = !CD_L ; (1 pterm, 1 signal) Chip5_current_state_3_.D = !CPB_L & Chip5_current_state_2_.Q ; (1 pterm, 2 signals) Chip5_current_state_3_.C = Chip2_Chip2_current_state_0_.Q ; (1 pterm, 1 signal) Chip5_current_state_3_.AR = !CD_L ; (1 pterm, 1 signal) Chip5_current_state_4_.D = !CPB_L & !Chip5_current_state_0_.Q & !Chip5_current_state_1_.Q & !Chip5_current_state_2_.Q # Chip5_current_state_3_.Q ; (2 pterms, 5 signals) Chip5_current_state_4_.C = Chip2_Chip2_current_state_0_.Q ; (1 pterm, 1 signal) Chip5_current_state_4_.AR = !CD_L ; (1 pterm, 1 signal) Chip5_current_state_5_.D = CPB_L & Chip5_current_state_4_.Q ; (1 pterm, 2 signals) Chip5_current_state_5_.C = Chip2_Chip2_current_state_0_.Q ; (1 pterm, 1 signal) Chip5_current_state_5_.AR = !CD_L ; (1 pterm, 1 signal) LED_CLK_1Hz_SQ.T = !Chip2_Chip5_present_state_2_.Q & !Chip2_Chip5_present_state_3_.Q & Chip2_Chip5_present_state_0_.Q & Chip2_Chip5_present_state_1_.Q & Chip2_Chip5_present_state_4_.Q & !Chip2_Chip3_present_state_1_.Q & !Chip2_Chip3_present_state_0_.Q & Chip2_Chip3_present_state_2_.Q & !Chip2_Chip1_present_state_3_.Q & !Chip2_Chip1_present_state_4_.Q & !Chip2_Chip1_present_state_5_.Q & !Chip2_Chip1_present_state_6_.Q & !Chip2_Chip1_present_state_10_.Q & !Chip2_Chip1_present_state_11_.Q & Chip2_Chip1_present_state_0_.Q & Chip2_Chip1_present_state_1_.Q & Chip2_Chip1_present_state_2_.Q & Chip2_Chip1_present_state_7_.Q & Chip2_Chip1_present_state_8_.Q & Chip2_Chip1_present_state_9_.Q & Chip2_Chip1_present_state_12_.Q ; (1 pterm, 21 signals) LED_CLK_1Hz_SQ.C = OSC_CLK_in ; (1 pterm, 1 signal) LED_CLK_1Hz_SQ.AR = !CD_L ; (1 pterm, 1 signal) LT_0_.T.X1 = CE & UD_L & LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q # CE & UD_L & LU_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q # CE & !UD_L & !LU_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q ; (3 pterms, 6 signals) LT_0_.T.X2 = CE & UD_L & LU_3_.Q & LT_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q & LT_2_.Q & LT_1_.Q & LT_0_.Q ; (1 pterm, 10 signals) LT_0_.C = N_9_i ; (1 pterm, 1 signal) LT_0_.AR = !CD_L ; (1 pterm, 1 signal) LT_1_.T = CE & !UD_L & !LU_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q & LT_2_.Q & !LT_0_.Q # CE & !UD_L & !LU_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q & LT_1_.Q & !LT_0_.Q # CE & !UD_L & !LU_3_.Q & LT_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q & !LT_0_.Q # CE & UD_L & LU_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q & !LT_2_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q & LT_1_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & LT_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q & LT_0_.Q ; (7 pterms, 10 signals) LT_1_.C = N_9_i ; (1 pterm, 1 signal) LT_1_.AR = !CD_L ; (1 pterm, 1 signal) LT_2_.T = CE & !UD_L & !LU_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q & !LT_1_.Q & !LT_0_.Q # CE & UD_L & LU_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q & !LT_2_.Q & LT_1_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & !LT_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q & LT_1_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & !LT_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q & LT_2_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q & LT_1_.Q & LT_0_.Q ; (5 pterms, 10 signals) LT_2_.C = N_9_i ; (1 pterm, 1 signal) LT_2_.AR = !CD_L ; (1 pterm, 1 signal) LT_3_.T = CE & !UD_L & !LU_3_.Q & LT_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q & !LT_2_.Q & !LT_1_.Q & !LT_0_.Q # CE & UD_L & LU_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q & LT_2_.Q & LT_1_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q & LT_2_.Q & LT_1_.Q & LT_0_.Q ; (3 pterms, 10 signals) LT_3_.C = N_9_i ; (1 pterm, 1 signal) LT_3_.AR = !CD_L ; (1 pterm, 1 signal) LU_0_.D = UD_L & LU_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q # CE & !LU_0_.Q # !CE & LU_0_.Q ; (3 pterms, 6 signals) LU_0_.C = N_9_i ; (1 pterm, 1 signal) LU_0_.AR = !CD_L ; (1 pterm, 1 signal) LU_1_.T = !( !LU_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q # LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q # UD_L & !LU_0_.Q # !UD_L & LU_0_.Q # !CE ) ; (5 pterms, 6 signals) LU_1_.C = N_9_i ; (1 pterm, 1 signal) LU_1_.AR = !CD_L ; (1 pterm, 1 signal) LU_2_.T = CE & !UD_L & LU_2_.Q & !LU_1_.Q & !LU_0_.Q # CE & UD_L & LU_1_.Q & LU_0_.Q # CE & !UD_L & LU_3_.Q & !LU_1_.Q & !LU_0_.Q ; (3 pterms, 6 signals) LU_2_.C = N_9_i ; (1 pterm, 1 signal) LU_2_.AR = !CD_L ; (1 pterm, 1 signal) LU_3_.T = CE & UD_L & !LU_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q # CE & !UD_L & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q # CE & UD_L & LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q ; (3 pterms, 6 signals) LU_3_.C = N_9_i ; (1 pterm, 1 signal) LU_3_.AR = !CD_L ; (1 pterm, 1 signal) N_9_i = !( Sel_pulse & Sel_filter & !Chip5_current_state_3_.Q & !Chip5_current_state_4_.Q & !Chip5_current_state_5_.Q # !Sel_pulse & !Sel_CLK_freq & !Chip2_Chip4_current_state_0_.Q # CPB_L & Sel_pulse & !Sel_filter # !Sel_pulse & Sel_CLK_freq & !LED_CLK_1Hz_SQ.Q ) ; (4 pterms, 9 signals) TC60 = CE & !UD_L & !LU_3_.Q & !LT_3_.Q & !LU_2_.Q & !LU_1_.Q & !LU_0_.Q & !LT_2_.Q & !LT_1_.Q & !LT_0_.Q # CE & UD_L & LU_3_.Q & LT_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q & LT_2_.Q & LT_1_.Q & LT_0_.Q # CE & UD_L & LU_3_.Q & !LT_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q & LT_2_.Q & !LT_1_.Q & LT_0_.Q ; (3 pterms, 10 signals) Ta = !( !LT_3_.Q & LT_2_.Q & !LT_1_.Q & !LT_0_.Q # LT_3_.Q & !LT_2_.Q & LT_1_.Q & LT_0_.Q # !LT_3_.Q & !LT_2_.Q & !LT_1_.Q & LT_0_.Q # LT_3_.Q & LT_2_.Q & !LT_1_.Q & LT_0_.Q ) ; (4 pterms, 4 signals) Tb = !( !LT_3_.Q & LT_2_.Q & !LT_1_.Q & LT_0_.Q # LT_2_.Q & LT_1_.Q & !LT_0_.Q # LT_3_.Q & LT_1_.Q & LT_0_.Q # LT_3_.Q & LT_2_.Q & !LT_0_.Q ) ; (4 pterms, 4 signals) Tc = !( !LT_3_.Q & !LT_2_.Q & LT_1_.Q & !LT_0_.Q # LT_3_.Q & LT_2_.Q & LT_1_.Q # LT_3_.Q & LT_2_.Q & !LT_0_.Q ) ; (3 pterms, 4 signals) Td = !( !LT_3_.Q & LT_2_.Q & !LT_1_.Q & !LT_0_.Q # LT_3_.Q & !LT_2_.Q & LT_1_.Q & !LT_0_.Q # !LT_2_.Q & !LT_1_.Q & LT_0_.Q # LT_2_.Q & LT_1_.Q & LT_0_.Q ) ; (4 pterms, 4 signals) Te = !( !LT_2_.Q & !LT_1_.Q & LT_0_.Q # !LT_3_.Q & LT_2_.Q & !LT_1_.Q # !LT_3_.Q & LT_0_.Q ) ; (3 pterms, 4 signals) Tf = !( LT_3_.Q & LT_2_.Q & !LT_1_.Q & LT_0_.Q # !LT_3_.Q & !LT_2_.Q & LT_1_.Q # !LT_3_.Q & !LT_2_.Q & LT_0_.Q # !LT_3_.Q & LT_1_.Q & LT_0_.Q ) ; (4 pterms, 4 signals) Tg = !( !LT_3_.Q & LT_2_.Q & LT_1_.Q & LT_0_.Q # LT_3_.Q & LT_2_.Q & !LT_1_.Q & !LT_0_.Q # !LT_3_.Q & !LT_2_.Q & !LT_1_.Q ) ; (3 pterms, 4 signals) Ua = !( !LU_3_.Q & LU_2_.Q & !LU_1_.Q & !LU_0_.Q # LU_3_.Q & !LU_2_.Q & LU_1_.Q & LU_0_.Q # !LU_3_.Q & !LU_2_.Q & !LU_1_.Q & LU_0_.Q # LU_3_.Q & LU_2_.Q & !LU_1_.Q & LU_0_.Q ) ; (4 pterms, 4 signals) Ub = !( !LU_3_.Q & LU_2_.Q & !LU_1_.Q & LU_0_.Q # LU_2_.Q & LU_1_.Q & !LU_0_.Q # LU_3_.Q & LU_1_.Q & LU_0_.Q # LU_3_.Q & LU_2_.Q & !LU_0_.Q ) ; (4 pterms, 4 signals) Uc = !( !LU_3_.Q & !LU_2_.Q & LU_1_.Q & !LU_0_.Q # LU_3_.Q & LU_2_.Q & LU_1_.Q # LU_3_.Q & LU_2_.Q & !LU_0_.Q ) ; (3 pterms, 4 signals) Ud = !( !LU_3_.Q & LU_2_.Q & !LU_1_.Q & !LU_0_.Q # LU_3_.Q & !LU_2_.Q & LU_1_.Q & !LU_0_.Q # !LU_2_.Q & !LU_1_.Q & LU_0_.Q # LU_2_.Q & LU_1_.Q & LU_0_.Q ) ; (4 pterms, 4 signals) Ue = !( !LU_2_.Q & !LU_1_.Q & LU_0_.Q # !LU_3_.Q & LU_2_.Q & !LU_1_.Q # !LU_3_.Q & LU_0_.Q ) ; (3 pterms, 4 signals) Uf = !( LU_3_.Q & LU_2_.Q & !LU_1_.Q & LU_0_.Q # !LU_3_.Q & !LU_2_.Q & LU_1_.Q # !LU_3_.Q & !LU_2_.Q & LU_0_.Q # !LU_3_.Q & LU_1_.Q & LU_0_.Q ) ; (4 pterms, 4 signals) Ug = !( !LU_3_.Q & LU_2_.Q & LU_1_.Q & LU_0_.Q # LU_3_.Q & LU_2_.Q & !LU_1_.Q & !LU_0_.Q # !LU_3_.Q & !LU_2_.Q & !LU_1_.Q ) ; (3 pterms, 4 signals)