-- Example of a synchronous 8-bit data register built using FSM style LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY data_register_8bits IS Port ( CLK : IN STD_LOGIC; CD : IN STD_LOGIC; LD : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); D_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ); END data_register_8bits; -- Internal desciption in FSM style: Three blocks --> State register, CC1 and CC2 ARCHITECTURE FSM_like OF data_register_8bits IS CONSTANT Reset : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; -- Internal wires --> in this case just the present and future state signals SIGNAL present_state,future_state: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN ------------------------- State register -- The only clocked block, which is essentially a set of D-type flip-flops in parellel -- The asynchronous reset has precedence over the CLK State_Register: PROCESS (CD, CLK,D_in) BEGIN IF CD = '1' THEN -- reset counter ( an asynchronous reset which we call "Clear Direct" present_state <= Reset; ELSIF (CLK'EVENT and CLK = '1') THEN -- Synchronous register (D-type flip-flop) present_state <= future_state; END IF; END PROCESS State_Register; -- CC1 ---------- Combinational circuit for calculating next state -- Generally, even for a simple FSM, this circuit will be complicated enough -- to use a "process" for writing it easier. CC1: PROCESS (present_state, D_in, LD) -- All the block inputs in the sensitivity list BEGIN IF LD='1' THEN future_state <= D_in; ELSE future_state <= present_state; END IF; END PROCESS CC1; --- CC2 ------------Combinational circuit for calculating the outputs -- There will be circuits like this register where the implementation is simply a buttfer -- We are interested in buffering the internal present state Q <= present_state; END FSM_like;