--------------------------------------------------- -- Synchronous frequency divider by 8 -- with asynchronous clear direct (CD) and count enable (CE) --------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter_mod8 IS PORT( CD,CLK,CE : IN std_logic; TC8 : OUT std_logic ); END counter_mod8; ARCHITECTURE FSM_style OF counter_mod8 IS CONSTANT Max_Count : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111"; CONSTANT Reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; SIGNAL present_state, future_state : std_logic_vector(2 DOWNTO 0); BEGIN ----------------------------- the only clocked block : the state register state_register: PROCESS (CD, CLK) BEGIN IF CD = '1' THEN -- reset counter present_state <= Reset; ELSIF (CLK'EVENT and CLK = '1') THEN -- Synchronous register (D-type flip-flop) present_state <= future_state; END IF; END PROCESS state_register; -- CC1: combinational system for calculating next state CS_1: PROCESS (present_state, CE) BEGIN IF CE = '1' THEN IF(present_state < Max_Count ) THEN future_state <= present_state + 1 ; ELSE future_state <= Reset; END IF; ELSE future_state <= present_state; -- count disable END IF; END PROCESS CS_1; -- combinational logic to determine the outputs -- CS2: TC8 <= '1' WHEN (present_state = Max_Count AND CE = '1') ELSE '0'; END FSM_style ;