-- Example of a single TFF in FSM style LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY T_Flip_Flop IS Port ( CLK : IN STD_LOGIC; CD : IN STD_LOGIC; T : IN STD_LOGIC; Q : OUT STD_LOGIC ); END T_Flip_Flop; -- Internal desciption in FSM style ARCHITECTURE FSM_like OF T_Flip_Flop IS CONSTANT Reset : STD_LOGIC := '0'; -- Internal wires SIGNAL present_state,future_state: STD_LOGIC := Reset; -- This thing of initialising these signals to the "Reset" state, -- is only an issue for the functional simulator. Once the circuit -- is synthesised, this thing is completely irrelevant. BEGIN ------------------------------ the only clocked block : the state register state_register: PROCESS (CD, CLK) BEGIN IF CD = '1' THEN -- reset counter present_state <= Reset; ELSIF (CLK'EVENT and CLK = '1') THEN -- Synchronous register (D-type flip-flop) present_state <= future_state; END IF; END PROCESS state_register; ------------------------- next state logic -- A T flip flop invert the output when T = 1, and do nothing when T = 0 CS_1: PROCESS (present_state, T) BEGIN IF T = '1' THEN future_state <= NOT (present_state); ELSE future_state <= present_state; END IF; END PROCESS CS_1; ------------------------- CS_2: combinational system for calculating extra outputs -- Very simple in this case, a buffer. Q <= present_state; END FSM_like;