-- Example of a binary synchronous counter -- using FSM style LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY Freq_Div_96 IS PORT( CD,CLK,CE : IN std_logic; TC96 : OUT std_logic ); END Freq_Div_96; -- Internal desciption in FSM style ARCHITECTURE FSM_like OF Freq_Div_96 IS CONSTANT Max_Count : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1011111"; -- terminal_count after 96 states CONSTANT Reset : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; -- Internal wires SIGNAL present_state,future_state: STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN ------------------------------ the only clocked block : the state register state_register: PROCESS (CD, CLK) BEGIN IF CD = '1' THEN -- reset counter present_state <= Reset; ELSIF (CLK'EVENT and CLK = '1') THEN -- Synchronous register (D-type flip-flop) present_state <= future_state; END IF; END PROCESS state_register; ------------------------- ESS state_registercombinational system for calculating next state CS_1: PROCESS (present_state, CE) BEGIN IF CE = '1' THEN IF(present_state < Max_Count ) THEN future_state <= present_state + 1 ; ELSE future_state <= Reset; END IF; ELSE future_state <= present_state; -- count disable END IF; END PROCESS CS_1; ------------------------- CS_2: combinational system for calculating extra outputs -------------------------- and outputing the present state (the actual count) TC96 <= '1' WHEN (present_state = Max_count AND CE = '1') ELSE '0'; --terminal count END FSM_like;