--Four_bit_shift_register LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY Shift_Data_Reg_4bits IS Port ( CLK : IN STD_LOGIC; CD : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0); RSI : IN STD_LOGIC; LSI : IN STD_LOGIC; Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); X : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); END Shift_Data_Reg_4bits; -- Internal desciption in FSM style ARCHITECTURE FSM_like OF Shift_Data_Reg_4bits IS CONSTANT Reset : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; -- Internal wires --> in this case just the present and future state signals SIGNAL present_state,future_state: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN ------------------------- State register -- The only clocked block, which is essentially a set of D-type flip-flops in parellel -- The asynchronous reset has precedence over the CLK State_Register: PROCESS (CD, CLK) BEGIN IF CD = '1' THEN -- reset counter ( an asynchronous reset which we call "Clear Direct" present_state <= Reset; ELSIF (CLK'EVENT and CLK = '1') THEN -- Synchronous register (D-type flip-flop) present_state <= future_state; END IF; END PROCESS State_Register; -- CC1 ---------- Combinational circuit for calculating next state -- Generally, even for a simple FSM, this circuit will be complicated enough -- for using a process in order to code it easier. CC1: PROCESS (present_state, X, S, RSI, LSI) BEGIN IF S = "11" THEN future_state <= X; ELSIF S="01" THEN future_state(0) <= present_state(1); future_state(1) <= present_state(2); future_state(2) <= present_state(3); future_state(3) <= RSI; ELSIF S="10" THEN future_state(3) <= present_state(2); future_state(2) <= present_state(1); future_state(1) <= present_state(0); future_state(0) <= LSI; ELSE future_state <= present_state; END IF; END PROCESS CC1; --- CC2 ------------Combinational circuit for calculating the outputs -- There will be circuits like ths counter where this circuit will be easily implemented -- just using equations Y <= present_state; END FSM_like;