--------------------------------------------------- -- Example of a good coding style: -- (hierarchical design using a top design and components) --------------------------------------------------- -- Structured oscillator clock frequency divider in 4 VHDL files -- Count Enable (CE) and asynchronous active-low clear direct (CD_L) -- 5 cascaded modules working in series to produce the following -- outputs from the HDW-LC4128V board's 1 MHz oscillator. -- OSC_CLK_out (divider by 1) --> 1 MHz -- CLK_20kHz (divider by 50 from the input OSC_CLK -- CLK_200Hz (divider by 100) -- CLK_4Hz (divider by 50 from the CLK_200Hz output) -- CLK_1Hz_SQUARED (divider by 4 using 2 T-FF to obtain a square wave from the pulsed input) --------------------------------------------------- --------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY OSC_FREQ_DIV IS PORT( CD_L,CE : IN std_logic; OSC_CLK_in : IN std_logic; OSC_CLK_out : OUT std_logic; CLK_20kHz : OUT std_logic; CLK_200Hz : OUT std_logic; CLK_4Hz : OUT std_logic; CLK_1Hz_SQUARED : OUT std_logic -- DISPLAYS : OUT std_logic_vector(14 downto 0; -- This DISPLAYS vector is an extra output only to blank unused LED's and segments -- In this example, only the decimal point in LED9 is used ); END OSC_FREQ_DIV; ARCHITECTURE schematic OF OSC_FREQ_DIV IS -- Components COMPONENT Freq_Div_50 IS PORT( CD,CLK,CE : IN std_logic; TC50 : OUT std_logic ); END COMPONENT; COMPONENT Freq_Div_100 IS PORT( CD,CLK,CE : IN std_logic; TC100 : OUT std_logic ); END COMPONENT; COMPONENT Freq_Div_2 IS PORT( CD,CLK,CE : IN std_logic; TC2 : OUT std_logic ); END COMPONENT; COMPONENT T_Flip_Flop IS PORT( CLK : IN STD_LOGIC; CD : IN STD_LOGIC; T : IN STD_LOGIC; Q : OUT STD_LOGIC ); END COMPONENT; -- Signals for connecting components together (just the internal wires) SIGNAL CD, OSC_CLK : std_logic; SIGNAL CE2, CE3, CE4, CE5 : std_logic; BEGIN -- Instantiation of components SS1 : Freq_Div_50 PORT MAP ( -- from component name => to signal or port name CLK => OSC_CLK, CD => CD, CE => CE, TC50 => CE2 ); SS2 : Freq_Div_100 PORT MAP ( -- from component name => to signal or port name CLK => OSC_CLK, CD => CD, CE => CE2, TC100 => CE3 ); SS3 : Freq_Div_50 PORT MAP ( -- from component name => to signal or port name CLK => OSC_CLK, CD => CD, CE => CE3, TC50 => CE4 ); SS4 : Freq_Div_2 PORT MAP ( -- from component name => to signal or port name CLK => OSC_CLK, CD => CD, CE => CE4, TC2 => CE5 ); SS5 : T_Flip_Flop PORT MAP ( -- from component name => to signal or port name CLK => OSC_CLK, CD => CD, T => CE5, Q => CLK_1Hz_SQUARED ); -- -- connections and logic between components -- The circuit's signals that have to be connected to input ports OSC_CLK <= OSC_CLK_in; CD <= NOT(CD_L); -- The output ports that have to be connected to signals OSC_CLK_out <= OSC_CLK; CLK_20kHz <= CE2; CLK_200Hz <= CE3; CLK_4Hz <= CE4; -- Displays OFF when high. In this fashion, only the SQUARED LED will be ON/OFF -- DISPLAYS <= "111111111111111"; END schematic ;