-- Copyright (C) 2020 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. -- *************************************************************************** -- This file contains a Vhdl test bench template that is freely editable to -- suit user's needs .Comments are provided in each section to help the user -- fill out necessary details. -- *************************************************************************** -- Generated on "12/07/2022 21:25:32" -- Vhdl Test Bench template for design : Shift_Reg_4bit -- -- Simulation tool : ModelSim-Altera (VHDL) -- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Shift_Reg_4bit_vhd_tst IS END Shift_Reg_4bit_vhd_tst; ARCHITECTURE Shift_Reg_4bit_arch OF Shift_Reg_4bit_vhd_tst IS -- constants -- signals SIGNAL CD : STD_LOGIC; SIGNAL CLK : STD_LOGIC; SIGNAL Din : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL LSI : STD_LOGIC; SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL RSI : STD_LOGIC; SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0); COMPONENT Shift_Reg_4bit PORT ( CD : IN STD_LOGIC; CLK : IN STD_LOGIC; Din : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LSI : IN STD_LOGIC; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); RSI : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ); END COMPONENT; -- Clock period definition to set the circuit's time resolution constant CLK_period : time := 1 us; -- 1 MHz -- Control inputs will be sampled 1 million times per second -- run simulations for 100 us BEGIN i1 : Shift_Reg_4bit PORT MAP ( -- list connections between master ports and signals CD => CD, CLK => CLK, Din => Din, LSI => LSI, Q => Q, RSI => RSI, S => S ); -- Clock process definition CLK_process :process begin CLK <= '0'; -- let's imagine a 33% duty cycle CLK oscillator wait for CLK_period*2/3; CLK <= '1'; wait for CLK_period*1/3; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for CLK_period*10; CD <= '0'; S <= "00"; Din <= "1010"; RSI <= '0'; LSI <= '0'; wait for CLK_period*1.23; CD <= '1'; -- Clear direct pulse wait for CLK_period*1.23; CD <= '0'; wait for CLK_period*2.55; -- Let's load parallel data Din <= "0111"; wait for CLK_period*2.55; S <= "11"; -- Load data pulse wait for CLK_period*2.55; S <= "00"; -- Do nothing, even meanwhile if Din changes wait for CLK_period*1.55; Din <= "1101"; wait for CLK_period*2.79; S <= "01"; -- Let's shift right for some CLKs wait for CLK_period*1.55; RSI <= '1'; wait for CLK_period*1.79; RSI <= '0'; wait for CLK_period*2.79; RSI <= '1'; wait for CLK_period*2.4; S <= "00"; -- Do nothing, wait for CLK_period*1.55; Din <= "0101"; wait for CLK_period*2.2; S <= "11"; -- Load data wait for CLK_period*2.79; S <= "10"; -- Let's shift left for some CLKs wait for CLK_period*1.55; LSI <= '1'; wait for CLK_period*1.79; LSI <= '0'; LSI <= '1'; wait for CLK_period*2.4; wait; end process; END Shift_Reg_4bit_arch;