-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:13:23 02/06/2012 -- Design Name: -- Module Name: D:/baixades/Counter_4bits/Counter_4bits_test_bench.vhd -- Project Name: Counter_4bits_project -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Counter_4bits -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Counter_4bits_test_bench IS END Counter_4bits_test_bench; ARCHITECTURE behavior OF Counter_4bits_test_bench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Counter_4bits PORT( CLK : IN std_logic; CD : IN std_logic; CE : IN std_logic; Q : OUT std_logic_vector(3 downto 0); TC10 : OUT std_logic ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal CD : std_logic := '0'; signal CE : std_logic := '0'; --Outputs signal Q : std_logic_vector(3 downto 0); signal TC10 : std_logic; -- Use the clock period which suits your application -- Clock period definitions, in this case a frequency of 1 MHz constant CLK_period : time := 1 us; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Counter_4bits PORT MAP ( CLK => CLK, CD => CD, CE => CE, Q => Q, TC10 => TC10 ); -- Clock process definitions -- Let's use all the simulation time relative to the "CLK_period" constant -- In this way it's easy to run simulations at different time scales. -- Only a constant needs to be modified. -- Start and wait for some time clk_signal : PROCESS BEGIN CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; END PROCESS clk_signal ; -- Stimulus process to be copied at the test bench file in the corresponding section: stimulus_signals: process begin wait for CLK_period*10.23; -- insert stimulus here CD <= '0'; CE <= '0'; wait for CLK_period*6.18; CD <= '1'; -- Clear direct wait for CLK_period*3.66; CD <= '0'; wait for CLK_period*3.33; CE <= '1'; -- Count enable wait for CLK_period*2.23; CE <= '0'; -- Count disable wait for CLK_period*8.23; CE <= '1'; -- Count enable wait for CLK_period*30.45; wait; end process stimulus_signals ; END;