-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 23:29:01 11/24/2017 -- Design Name: -- Module Name: L:/CSD/1718Q1/P7/Counter_mod16/Counter_mod16_tb.vhd -- Project Name: Counter_mod16_prj -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Counter_mod16 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Counter_mod16_tb IS END Counter_mod16_tb; ARCHITECTURE behavior OF Counter_mod16_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Counter_mod16 PORT( CLK : IN std_logic; CD : IN std_logic; LD : IN std_logic; CE : IN std_logic; UD_L : IN std_logic; Din : IN std_logic_vector(3 downto 0); Q : OUT std_logic_vector(3 downto 0); TC16 : OUT std_logic ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal CD : std_logic := '0'; signal LD : std_logic := '0'; signal CE : std_logic := '0'; signal UD_L : std_logic := '0'; signal Din : std_logic_vector(3 downto 0) := (others => '0'); --Outputs signal Q : std_logic_vector(3 downto 0); signal TC16 : std_logic; -- Clock period definitions constant CLK_period : time := 10 us; -- f_CLK = 100 kHz BEGIN -- Instantiate the Unit Under Test (UUT) uut: Counter_mod16 PORT MAP ( CLK => CLK, CD => CD, LD => LD, CE => CE, UD_L => UD_L, Din => Din, Q => Q, TC16 => TC16 ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for CLK_period*10; CD <= '0'; LD <= '0'; CE <= '0'; UD_L <= '0'; Din <= "0101"; wait for CLK_period*3.3; -- Clear direct pulse: CD <= '1'; wait for CLK_period*1.23; CD <= '0'; wait for CLK_period*3.23; -- Register parallel data Din <= "1110"; wait for CLK_period*3.23; LD <= '1'; wait for CLK_period*2.23; Din <= "0010"; wait for CLK_period*3.23; LD <= '0'; wait for CLK_period*3.23; -- Let's count up for a while UD_L <= '1'; CE <= '1'; wait for CLK_period*25.1; -- Let's count down for a while UD_L <= '0'; CE <= '1'; wait for CLK_period*8.1; -- Register parallel data Din <= "1001"; wait for CLK_period*3.23; LD <= '1'; wait for CLK_period*2.23; Din <= "0010"; wait for CLK_period*3.23; LD <= '0'; wait for CLK_period*3.23; -- Let's count up for a while UD_L <= '1'; CE <= '1'; wait for CLK_period*25.1; wait; end process; END;