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-- Project P8  - CSD 
-- https://digsys.upc.edu                          
-- Component Counter_BCD_mod60 to count up to 59 and down to 00
-- If the CLK is 1 Hz, it counts up to one minute

-- Strategy: Plan C2. Adapt the Hour_Counter in P7:
-- https://digsys.upc.edu/csd/P07/P7.html to be the Counter_BCD_mod60
-- TC60 is '1' only when CE = 1, and (UD_L = 1 and 59) or (UD_L = 0 and 00) 

-- This VHDL files is a direct translation of the schematic in Fig. 3 at: 
-- https://digsys.upc.edu/csd/P07/Counter_BCD_mod60/Counter_BCD_mod60.html
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LIBRARY ieee;
USE  IEEE.STD_LOGIC_1164.all;

ENTITY Counter_BCD_mod60 IS
	PORT (
		UD_L, CE, CD, CLK	: IN	STD_LOGIC;
		D_Tens, D_Units		: OUT	STD_LOGIC_VECTOR (3 DOWNTO 0);
		TC60				: OUT	STD_LOGIC
	 );
END Counter_BCD_mod60;

ARCHITECTURE hierarchical_structure OF Counter_BCD_mod60 IS
	
-- The elemental components to be used:
 	COMPONENT Counter_mod16 IS  
      Port (	
			CLK				: IN	STD_LOGIC;
			CD					: IN	STD_LOGIC;
			LD, CE, UD_L	: IN	STD_LOGIC;			
			Din				: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			Q					: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0);
			TC16				: OUT	STD_LOGIC
		);      
	END COMPONENT;

	COMPONENT Quad_MUX_2 IS  
		PORT(
			CH0	    :IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
			CH1	    :IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
			E		:IN STD_LOGIC;
			Y		:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
			S		:IN STD_LOGIC 
		);
	END COMPONENT;
	

-- Now the signals (wires and cables) to build the schematic 

	SIGNAL	D0T, D0U, D9U			: STD_LOGIC;
	SIGNAL	D00, D59				: STD_LOGIC;
	SIGNAL	CET, ST, LDU, LDT, SU	: STD_LOGIC;
	SIGNAL	DT, DU, P, K			: STD_LOGIC_VECTOR (3 downto 0);

BEGIN

-- Instantiation of up to 4 basic 1-bit adders:

	Chip1	: Counter_mod16
		PORT MAP (
	-- from component name 	=> to signal or port name		
			CLK		    =>	CLK,
			CD			=>	CD,				
			LD			=>	LDT,
			CE			=>	CET,
			UD_L		=>	UD_L,
			Din		    =>	DT,
			Q			=>	P,
			TC16		=>	D0T
		);
			
	Chip2	: Counter_mod16
		PORT MAP (
	-- from component name 	=> to signal or port name		
			CLK		    =>	CLK,
			CD			=>	CD,				
			LD			=>	LDU,
			CE			=>	CE,
			UD_L		=>	UD_L,
			Din		    =>	DU,
			Q			=>	K,
			TC16		=>	D0U
		);
		
	Chip3	: Quad_MUX_2
		PORT MAP (
	-- from component name 	=> to signal or port name		
			E			=>	'1',
			Ch0	        =>	"0000", -- Truncate D_Units when counting up and 9
			Ch1		    =>	"1001", -- Truncate D_Units when counting down and 0
			S			=>	SU,
			Y			=>	DU
		);

		
	Chip4	: Quad_MUX_2
		PORT MAP (
	-- from component name 	=> to signal or port name		
			E			=>	'1',
			Ch0		    =>	"0000", -- Truncate D_Tens when counting up and 5
			Ch1		    =>	"0101", -- Truncate D_Tens when counting down and 0
			S			=>	ST,
			Y			=>	DT
		);

	
-- Equations and logic gates for the internal signals: 
		D00 <= D0U and D0T;
		D59 <= '1' when UD_L = '1' and CE = '1' and P = "0101" and K = "1001" ELSE '0';
		D9U	<= '1' when UD_L = '1' and CE = '1' and K = "1001" ELSE '0';
		
		SU	<= D0U or D00;
		LDU	<= D00 or D59 or D9U or D0U;

		CET	<= D0U or D9U; 
		
		ST	<= D00;	
		LDT	<= D00 or D59;

		
-- Outputs 		
		TC60	<= LDT;
		D_Tens 	<= P;
		D_Units	<= K;
		
		
END hierarchical_structure;