-------------------------------------------------------------------------------- -- UPC - EETAC - EEL - CSD: Digital Circuits and Systems - DIGSYS -------------------------------------------------------------------------------- -- LAB6 example tutorial on prototyping: Light control top -- Target board: DE10-Lite Terasic -- Target PLD: MAX10 10M50DAF484C7 -- Plan C2: FSM and some additional components for: -- Adapting buttons and LED -- Generating CLK signal from board external oscillator -- 7-segment decoding for displaying FSM internal states. -- Reference and schematic at: https://digsys.upc.edu/csd/P06/lab06/lab6.html -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY Light_Control_top IS Port ( OSC_CLK_in : IN std_logic; CD_L : IN STD_LOGIC; B_L : IN STD_LOGIC; Z : OUT STD_LOGIC; HEX4 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); ---- All LED not used connected to '0' LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8 : OUT STD_LOGIC ); END Light_Control_top; -- The desciption of the proposed schematic -- ARCHITECTURE schematic OF Light_Control_top IS COMPONENT Light_Control IS -- This is the FSM Port ( CLK : IN STD_LOGIC; B : IN STD_LOGIC; CD : IN STD_LOGIC; Z : OUT STD_LOGIC; -- Extra output to monitor the current state CS_out : OUT STD_LOGIC_VECTOR(2 downto 0) ); END COMPONENT; COMPONENT CLK_Generator IS PORT( OSC_CLK_in : IN STD_LOGIC; CD : IN STD_LOGIC; CE : IN STD_LOGIC; CLK_200Hz_SQ : OUT STD_LOGIC ); end COMPONENT; COMPONENT HEX_7seg_DECODER IS PORT ( X_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); BI_L : IN STD_LOGIC; A_L, B_L, C_L, D_L, E_L, F_L, G_L : OUT STD_LOGIC ); end COMPONENT; -- Signals for connecting components together (the wires) SIGNAL CD, CLK, B : std_logic; Signal CS : STD_LOGIC_VECTOR(2 downto 0); BEGIN -- Instantiation of components Chip1 : Light_Control -- from component name => to signal or port name PORT MAP ( CLK => CLK, CD => CD, B => B, CS_out => CS, Z => Z ); Chip2 : CLK_Generator -- from component name => to signal or port name PORT MAP ( CD => CD, CE => '1', OSC_CLK_in => OSC_CLK_in, CLK_200Hz_SQ => CLK ); Chip3 : HEX_7seg_decoder -- from component name => to signal or port name PORT MAP ( X_IN(3) => '0', X_IN(2 downto 0)=> CS, BI_L => '1', A_L => HEX4(0), B_L => HEX4(1), C_L => HEX4(2), D_L => HEX4(3), E_L => HEX4(4), F_L => HEX4(5), G_L => HEX4(6) ); -- extra buffers to adapt the board hardware CD <= not (CD_L); -- The board has active-low push-buttons B <= not (B_L); -- All LED not used connected to '0': LED0 <= '0'; LED1 <= '0'; LED2 <= '0'; LED3 <= '0'; LED4 <= '0'; LED5 <= '0'; LED6 <= '0'; LED7 <= '0'; LED8 <= '0'; END schematic;