-------------------------------------------------------------------------------- -- Tutorial P5. An example of the implememtation of the RS latch -- using logic equations (structural) -only NOR -- UPC - EETAC - CSD -- http://digsys.upc.edu -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY RS_latch IS PORT ( R, S : IN STD_LOGIC; Q : OUT STD_LOGIC ); END RS_latch; ARCHITECTURE logic_equations OF RS_latch IS SIGNAL W, Z : STD_LOGIC; -- This is the feedback wire BEGIN Z <= W nor S; W <= Z nor R; Q <= W; END logic_equations;