-- UPC - EETAC- EEL - Digital Circuits and Systems (CSD) -- Example of a D-FF -- Written as a simple process ------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY D_FF IS Port ( CLK, CD, D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END D_FF; ARCHITECTURE DFF_register OF D_FF IS BEGIN state_register: PROCESS (CD, CLK, D) BEGIN IF CD = '1' THEN -- Asynchronous reset (Clear direct) Q <= '0'; ELSIF (CLK'EVENT and CLK = '1') THEN -- Synchronous register (D-type flip-flop) Q <= D; END IF; END PROCESS state_register; END DFF_register;