-- Copyright (C) 2020 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. -- *************************************************************************** -- This file contains a Vhdl test bench template that is freely editable to -- suit user's needs .Comments are provided in each section to help the user -- fill out necessary details. -- *************************************************************************** -- Generated on "07/11/2022 11:25:10" -- Vhdl Test Bench template for design : Adder_16bit -- -- Simulation tool : ModelSim-Altera (VHDL) -- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Adder_16bit_vhd_tst IS END Adder_16bit_vhd_tst; ARCHITECTURE Adder_16bit_arch OF Adder_16bit_vhd_tst IS -- constants C:/CSD/P4/Adder_16bit_RC/Adder_16bit_tb.vhd -- signals SIGNAL A : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL B : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL Cin : STD_LOGIC; SIGNAL Cout : STD_LOGIC; SIGNAL S : STD_LOGIC_VECTOR(15 DOWNTO 0); COMPONENT Adder_16bit PORT ( A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); Cin : IN STD_LOGIC; Cout : BUFFER STD_LOGIC; S : BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; -- Time -- constant Min_Pulse : time := 25ns; -- Thus, we will run for 1 us constant Min_Pulse : time := 20ns; -- Thus, we will run for 1 us BEGIN i1 : Adder_16bit PORT MAP ( -- list connections between master ports and signals A => A, B => B, Cin => Cin, Cout => Cout, S => S ); -- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN -- Circuit initialisation period (do nothing). wait for 100 ns; wait for Min_Pulse*2.34; -- Let's start the stimulus activity A <= "0000000000000000"; -- 0 + 0 + 1 = 1 B <= "0000000000000000"; Cin <= '1'; wait for Min_Pulse; A <= "0111011000100101"; -- 30245 + 62400 + 1 = 92646 B <= "1111001111000000"; Cin <= '1'; wait for Min_Pulse; A <= "1111111111111111"; -- 65535 + 33333 + 0 = 98868 B <= "1000001000110101"; Cin <= '1'; wait for Min_Pulse; A <= "0000000000000000"; -- 0 + 65535 + 1 = 65536 B <= "1111111111111111"; -- = 1 0000 0000 0000 0000 Cin <= '1'; wait for Min_Pulse; A <= "1010101010101010"; -- 43690 + 21845 + 0 = 65535 B <= "0101010101010101"; -- = 0 1111 1111 1111 1111 Cin <= '0'; wait for Min_Pulse; A <= "0000000000000000"; -- 0 + 65535 + 1 = 65536 B <= "1111111111111111"; -- = 1 0000 0000 0000 0000 Cin <= '1'; wait for Min_Pulse; -- We will switch all output bits simply switching Cin A <= "0111111111111111"; -- 32767 + 32768 + 0 = 65535 B <= "1000000000000000"; -- = 0 1111 1111 1111 1111 Cin <= '0'; wait for Min_Pulse; Cin <= '1'; wait for Min_Pulse; Cin <= '0'; wait for Min_Pulse; Cin <= '1'; wait for Min_Pulse; wait; -- will wait forever END PROCESS; -- *** End Test Bench - User Defined Section *** END Adder_16bit_arch;