-------------------------------------------------------------------------------- -- UPC - EETAC - CSD - digsys.upc.edu -------------------------------------------------------------------------------- -- P3. E. Ones_counter_4bit -- Plan: Hierachical approach. Implementing logic functions using decoders -- Reference schematic at: -- https://digsys.upc.edu/csd/P03/ones_counter_4bit/ones_counter_4bit.html -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY ones_counter_4bit IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END ones_counter_4bit; ARCHITECTURE hierarchical_structure OF ones_counter_4bit IS -- The elemental component to be used: COMPONENT Dec4_16 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); E : IN STD_LOGIC; Y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; -- Signals -- This wire is named "m(15..0) because every output is a minterm SIGNAL m : STD_LOGIC_VECTOR (15 DOWNTO 0); BEGIN -- Instantiation of up to 4 basic 1-bit adders: Chip1 : Dec4_16 PORT MAP ( -- from component name => to signal or port name D => D, E => '1', -- let's maintain it always enabled Y => m ); -- Other circuits and equations: The generation of the three outputs Y(2) <= m(15); Y(1) <= m(3) or m(5)or m(6)or m(7)or m(9)or m(10)or m(11)or m(12)or m(13)or m(14); Y(0) <= m(1) or m(2)or m(4)or m(7)or m(8)or m(11)or m(13)or m(14); END hierarchical_structure;