-------------------------------------------------------------------------------- -- An example of using the method of decoders for implementing logic functions --------------------------------------------------- -- Adder_1bit structural: using components -- Exercise P3 - CSD -- http://digsys.upc.edu -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY Adder_1bit IS PORT ( Ai, Bi, Ci : IN STD_LOGIC; So, Co : OUT STD_LOGIC ); END Adder_1bit; ARCHITECTURE hierarchical_structure OF Adder_1bit IS -- The elemental components to be used: COMPONENT Dec_3_8 IS PORT ( E : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(2 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; -- Signals: the internal wires or cables SIGNAL m : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN -- Instantiation of the decoder: Chip1 : Dec_3_8 PORT MAP ( -- from component name => to signal or port name E => '1', -- Always enabled D(2) => Ai, D(1) => Bi, D(0) => Ci, Y => m ); -- Other circuits and equations: Co <= m(3) or m(5) or m(6) or m(7); So <= m(1) or m(2) or m(4) or m(7); END hierarchical_structure;