-------------------------------------------------------------------------------- -- A standard circuit Enc_10_4 : Encoder from 10 keys to 4-bit binary (or BCD) -- Behavioural approach (Plan B) -- This is the translation of the schematic representing the truth table -- The schematic is Fig. 6 in this page: -- https://digsys.upc.edu/csd/P02/enc_10_4B/Enc_10_4B.html --------------------------------------------------- -- Project P2 - CSD : standard logic circuits in VHDL -- http://digsys.upc.edu -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- To be able to translate "std_match" entity Enc_10_4 is port ( D_L : in STD_LOGIC_VECTOR(9 downto 0); Ei_L : in STD_LOGIC; Y : out STD_LOGIC_VECTOR(3 downto 0); Eo_L : out STD_LOGIC; GS_L : out STD_LOGIC ); end Enc_10_4; -- The connections to the truth table artefact -- Circuit truth table is described in Fig. 2 at: -- https://digsys.upc.edu/csd/P02/enc_10_4B/Enc_10_4B.html architecture Truth_table of Enc_10_4 is SIGNAL Xin : STD_LOGIC_VECTOR (10 downto 0); SIGNAL Yout : STD_LOGIC_VECTOR (5 downto 0); begin -- Xin (10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) --> Ei_L D_L(9) ... D_L(0) -- Yout(5, 4, 3, 2, 1, 0) --> GS_L Y(3) Y(2) Y(1) Y(0) Eo_L -- This is the very convenient statement to be used when "don't care" inputs Yout <= "100001" when std_match(Xin,"1----------") else -- disabled "100000" when std_match(Xin,"01111111111") else -- no key pressed "000001" when std_match(Xin,"01111111110") else -- Key 0 clicked "000011" when std_match(Xin,"0111111110-") else -- Key 1 clicked "000101" when std_match(Xin,"011111110--") else -- Key 2 clicked "000111" when std_match(Xin,"01111110---") else -- Key 3 clicked "001001" when std_match(Xin,"0111110----") else -- Key 4 clicked "001011" when std_match(Xin,"011110-----") else -- Key 5 clicked "001101" when std_match(Xin,"01110------") else -- Key 6 clicked "001111" when std_match(Xin,"0110-------") else -- Key 7 clicked "010001" when std_match(Xin,"010--------") else -- Key 8 clicked "010011" when std_match(Xin,"00---------"); -- Key 9 clicked -- WRONG TRANSLATION !! Watch RTL schematic after synthesis -- The simple buffers to attach the inputs and outputs to the truth table -- Input connection Xin(10) <= Ei_L; Xin(9 downto 0) <= D_L; -- This is a block of 10 buffers -- Output connection GS_L <= Yout(5); Y <= Yout(4 downto 1); -- this is like a block of 4 buffers Eo_L <= Yout(0); end Truth_table;