-------------------------------------------------------------------------------- -- An example of a chip design: MUX_8 (type 74153) -------------------------------------------------------------------------------- -- MUX_8 using plan B behavioural approach where the truth table is written in -- VHDL by means of a flowchart (Version 3) using PROCESS statement. -- This VHDL file is the translation of schematic: -- https://digsys.upc.edu/csd/P02/lab02/img_planB_V1_V_3.jpg --------------------------------------------------- -- Exercise P2 - CSD -- http://digsys.upc.edu -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ENTITY MUX_8 IS PORT ( -- Data channels declared as individual wires -- Declaring them as a vector Ch(7..0) will change the symbol Ch7, Ch6, Ch5, Ch4 : IN STD_LOGIC; -- 1 bit per channel Ch3, Ch2, Ch1, Ch0 : IN STD_LOGIC; -- 1 bit per channel -- S(2..0) to select 8 channels declared as a vector S : IN STD_LOGIC_VECTOR (2 downto 0); E_L : IN STD_LOGIC; Y : OUT STD_LOGIC; Y_L : OUT STD_LOGIC ); END MUX_8; ARCHITECTURE truth_table_flowchart3 OF MUX_8 IS -- The wire where to connect the outputs SIGNAL Q : STD_LOGIC; BEGIN PROCESS ( E_L, S, Ch7,Ch6,Ch5,Ch4,Ch3,Ch2,Ch1,Ch0) BEGIN IF E_L = '1' THEN Q <= '0'; -- disable (this is half of the table (2048 rows) ELSE -- This is the MUX_8 function IF S = "000" THEN Q <= Ch0; ELSIF S = "001" THEN Q <= Ch1; ELSIF S = "010" THEN Q <= Ch2; ELSIF S = "011" THEN Q <= Ch3; ELSIF S = "100" THEN Q <= Ch4; ELSIF S = "101" THEN Q <= Ch5; ELSIF S = "110" THEN Q <= Ch6; ELSE Q <= Ch7; END IF ; END IF ; END PROCESS; Y <= Q; -- This is a non-inverter buffer Y_L <= not(Q); -- This is an inverter END truth_table_flowchart3;