-------------------------------------------------------------------------------- -- An example of a chip design: MUX8 (type 74153) -------------------------------------------------------------------------------- -- Exercise P2 - CSD -- http://digsys.upc.edu --------------------------------------------------- -- MUX8 structural flat design: A single-file circuit containing smaller blocks -- like MUX4 and MUX2 and extra logic logic. -- Method C1 in P2: http://digsys.upc.edu/csd/P02/P2.html -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY MUX_8 IS PORT ( Ch7, Ch6, Ch5, Ch4 : IN STD_LOGIC; -- 1 bits per channel Ch3, Ch2, Ch1, Ch0 : IN STD_LOGIC; -- 1 bits per channel S : IN STD_LOGIC_VECTOR (2 downto 0);-- to select 8 E_L : IN STD_LOGIC; -- enable active low Y, Y_L : OUT STD_LOGIC ); END MUX_8; ARCHITECTURE flat_structure OF MUX_8 IS SIGNAL K, P, Q : STD_LOGIC; -- internal wires BEGIN -- Equations using a sum of products (SoP) -- The ones in the truth table -------------------------------------------------------------------------------- -- This is a structural description in SoP of the MUX_4 (SoP)(Chip2 ) K <= (not(S(1)) and not (S(0))and Ch0) or (not(S(1)) and S(0) and Ch1) or (S(1) and not(S(0)) and Ch2) or (S(1) and S(0) and Ch3); -- The same structural description in SoP of the MUX_4 (Chip1 in the schematic) P <= (not(S(1)) and not (S(0))and Ch4) or (not(S(1)) and S(0) and Ch5) or (S(1) and not(S(0)) and Ch6) or (S(1) and S(0) and Ch7); -- And this is a version of the MUX_8 using its algorithm: Q <= K when (S(2) ='0' and E_L = '0') else P when (S(2) ='1' and E_L = '0') else '0'; -- And the last buffer and inverter for the output: Y <= Q; Y_L <= not(Q); -- Realise the difficulty and the complication of this method C1 -- "hiearchical flat design" even for this simple circuits. We'll replace it by -- the method C2 (using components and signals in a multiple file project) which -- is by far easier. See for instance the 4-bit adder in P3: -- http://digsys.upc.es/csd/P03/P3_T/P3_tut_4bit_adder.html END flat_structure;