-- Copyright (C) 2020 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. -- *************************************************************************** -- This file contains a Vhdl test bench template that is freely editable to -- suit user's needs .Comments are provided in each section to help the user -- fill out necessary details. -- *************************************************************************** -- Generated on "05/09/2021 19:07:08" -- Vhdl Test Bench template for design : Dual_MUX_4 -- -- Simulation tool : ModelSim-Altera (VHDL) -- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Dual_MUX_4_vhd_tst IS END Dual_MUX_4_vhd_tst; ARCHITECTURE Dual_MUX_4_arch OF Dual_MUX_4_vhd_tst IS -- constants -- signals SIGNAL Ch0 : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL Ch1 : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL Ch2 : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL Ch3 : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL E_L : STD_LOGIC; SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL Y : STD_LOGIC_VECTOR(1 DOWNTO 0); COMPONENT Dual_MUX_4 PORT ( Ch0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Ch1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Ch2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Ch3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); E_L : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END COMPONENT; constant Min_Pulse : time := 25.5 us; -- run simulation for 400 us BEGIN i1 : Dual_MUX_4 PORT MAP ( -- list connections between master ports and signals Ch0 => Ch0, Ch1 => Ch1, Ch2 => Ch2, Ch3 => Ch3, E_L => E_L, S => S, Y => Y ); -- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN -- Circuit initialisation period (do nothing). wait for 100 ns; wait for Min_Pulse*1.5; -- Let's start the stimulus activity: E_L <= '1'; Ch0 <= "11"; Ch1 <= "10"; Ch2 <= "01"; Ch3 <= "00"; S <= "00"; wait for Min_Pulse*2.2; -- Let's start the stimulus activity: E_L <= '0'; wait for Min_Pulse*2.2; Ch0 <= "00"; Ch1 <= "01"; Ch2 <= "10"; Ch3 <= "11"; S <= "01"; wait for Min_Pulse*1.2; Ch0 <= "01"; Ch1 <= "10"; Ch2 <= "11"; Ch3 <= "00"; S <= "10"; wait for Min_Pulse*1.2; Ch0 <= "00"; Ch1 <= "01"; Ch2 <= "10"; Ch3 <= "11"; S <= "11"; wait for Min_Pulse*3.3; E_L <= '1'; wait for Min_Pulse*2.4; E_L <= '0'; wait for Min_Pulse*1.6; Ch0 <= "10"; Ch1 <= "11"; Ch2 <= "00"; Ch3 <= "11"; S <= "00"; wait for Min_Pulse*2.5; wait; -- will wait forever END PROCESS; -- *** End Test Bench - User Defined Section ***+ END Dual_MUX_4_arch;