-------------------------------------------------------------------------------- -- UPC - EETAC - CSD - digsys.upc.edu -------------------------------------------------------------------------------- -- A standard circuit Dec_4_16: Binary decoder 4 to 16 (DEC4:16) -- Plan B: behavioural approach. This is the translation of the schematic -- capturing the complete truth table in this page (Fig. 3): -- https://digsys.upc.edu/csd/P02/DEC/Dec_4_16B/Dec_4_16.html -- Project P2: standard logic circuits in VHDL -- http://digsys.upc.edu -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY Dec_4_16 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); E : IN STD_LOGIC; Y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END Dec_4_16; ARCHITECTURE truth_table OF Dec_4_16 IS -- This signal is for grouping all the inputs into a single input vector cable: signal X_in: STD_LOGIC_VECTOR (4 downto 0); BEGIN PROCESS (X_in) BEGIN CASE X_in IS -- E D3 D2 D1 D0 Y(15..0) -- ------------- ----------------------- WHEN "10000" => -- decoding 0 Y <= "0000000000000001"; WHEN "10001" => -- decoding 1 Y <= "0000000000000010"; WHEN "10010" => -- decoding 2 Y <= "0000000000000100"; WHEN "10011" => -- decoding 3 Y <= "0000000000001000"; WHEN "10100" => -- Y <= "0000000000010000"; WHEN "10101" => -- Y <= "0000000000100000"; WHEN "10110" => -- Y <= "0000000001000000"; WHEN "10111" => -- Y <= "0000000010000000"; WHEN "11000" => -- Y <= "0000000100000000"; WHEN "11001" => -- Y <= "0000001000000000"; WHEN "11010" => -- Y <= "0000010000000000"; WHEN "11011" => -- Y <= "0000100000000000"; WHEN "11100" => -- Y <= "0001000000000000"; WHEN "11101" => -- Y <= "0010000000000000"; WHEN "11110" => -- Y <= "0100000000000000"; WHEN "11111" => -- decoding 15 Y <= "1000000000000000"; WHEN Others => -- disable the chip Y <= "0000000000000000"; END CASE; END PROCESS; -- Extra logic is required to connect the input buffers -- that adapt the inputs to the truth table artefact X_in(4) <= E; X_in(3 downto 0) <= D; END truth_table;