------------------------------------------------------------------------------- -- An example of the P1 - Section B: Designing circuit based on logic gates -- Circuit_Q1 based on Circuit_Q description as canonical sum of minterms -- Q = f(S1, S0, A, B) = m1+m2+m3+m7+m8+m11+m13+m15 -- This is also an exercise to introduce the VHDL language and EDA tools --------------------------------------------------- -- CSD projects P1 -- http://digsys.upc.edu ------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY Circuit_Q1 IS PORT ( S1, S0 : IN STD_LOGIC; A, B : IN STD_LOGIC; Q : OUT STD_LOGIC ); END Circuit_Q1; ARCHITECTURE canonical_sum_of_minterms OF Circuit_Q1 IS BEGIN -- This is its translation to VHDL: -- m1+m2+m3+m7+m8+m11+m13+m15 Q <= ( ( not(S1) and not(S0) and not(A) and B ) or --- m1 ( not(S1) and not(S0) and A and not(B) ) or --- m2 ( not(S1) and not(S0) and A and B ) or --- m3 ( not(S1) and S0 and A and B ) or --- m7 ( S1 and not(S0) and not(A) and not(B) ) or --- m8 ( S1 and not(S0) and A and B ) or --- m11 ( S1 and S0 and not(A) and B ) or --- m13 ( S1 and S0 and A and B ) --- m15 ); END canonical_sum_of_minterms;