m255
K4
z2
!s11e vcom 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/DEE/Dimmer/FPGA_PWM_top
Ehard_block
Z1 w1768254290
Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1
Z3 DPx11 fiftyfivenm 21 fiftyfivenm_atom_pack 0 22 OTUTkBjTeYVegmIWhVi3N0
Z4 DPx4 ieee 12 vital_timing 0 22 J>EBealN09f8GzldA[z2>3
Z5 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z6 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
Z7 DPx11 fiftyfivenm 22 fiftyfivenm_components 0 22 C5K^h=:j[4HI?HO^UkN3:2
!i122 9
R0
Z8 8C:/DEE/Dimmer/FPGA_PWM_top/simulation/modelsim/PWM_top.vho
Z9 FC:/DEE/Dimmer/FPGA_PWM_top/simulation/modelsim/PWM_top.vho
l0
L35 1
VoIY9CfLHaCo>=<9ZVlU==2
!s100 3A]XnMhF<;9mKUe5mn3aM1
Z10 OV;C;2020.1;71
32
Z11 !s110 1768256233
!i10b 1
Z12 !s108 1768256233.000000
Z13 !s90 -reportprogress|300|-work|work_gate_level|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/simulation/modelsim/PWM_top.vho|
Z14 !s107 C:/DEE/Dimmer/FPGA_PWM_top/simulation/modelsim/PWM_top.vho|
!i113 1
Z15 o-work work_gate_level -2002 -explicit
Z16 tExplicit 1 CvgOpt 0
Astructure
R2
R3
R4
R5
R6
R7
Z17 DEx4 work 10 hard_block 0 22 oIY9CfLHaCo>=<9ZVlU==2
!i122 9
l76
Z18 L54 28
Z19 V]NZ1Jn`3251e;XDGe7J1V0
Z20 !s100 >:Wi^nX[YiN=@>>JC6K_83
R10
32
R11
!i10b 1
R12
R13
R14
!i113 1
R15
R16
Epwm_top
R1
R3
R7
R2
Z21 DPx6 altera 11 dffeas_pack 0 22 dc5N=DKXMMTVYdUQ@D3FA2
R4
R5
R6
Z22 DPx6 altera 28 altera_primitives_components 0 22 ca:ehlQAg4;_gVV:^8MAg3
!i122 9
R0
R8
R9
l0
L91 1
V8=^=N3F:RhWkULh@^6L;V0
!s100 @DO8DI>_;fPg76IzE`gGl0
R10
32
R11
!i10b 1
R12
R13
R14
!i113 1
R15
R16
Astructure
R3
R7
R2
R21
R4
R5
R6
R22
DEx4 work 7 pwm_top 0 22 8=^=N3F:RhWkULh@^6L;V0
!i122 9
l290
L120 2576
VIgJRWX`6aY>Ime]NkR7I=2
!s100 ZNSGj6LIcZh5Yb<^mooFR3
R10
32
!s110 1768256234
!i10b 1
R12
R13
R14
!i113 1
R15
R16
Epwm_top_vhd_tst
Z23 w1768254678
R5
R6
!i122 8
R0
Z24 8C:/DEE/Dimmer/FPGA_PWM_top/PWM_top_tb.vhd
Z25 FC:/DEE/Dimmer/FPGA_PWM_top/PWM_top_tb.vhd
l0
L31 1
VUFXUnaNSUnKBGUMZZYS4R2
!s100 <2FDlQ_Oef7:X>z:;>2Uz0
R10
32
R11
!i10b 1
R12
Z26 !s90 -reportprogress|300|-work|work_gate_level|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/PWM_top_tb.vhd|
Z27 !s107 C:/DEE/Dimmer/FPGA_PWM_top/PWM_top_tb.vhd|
!i113 1
R15
R16
Apwm_top_arch
R5
R6
DEx4 work 15 pwm_top_vhd_tst 0 22 UFXUnaNSUnKBGUMZZYS4R2
!i122 8
l62
L34 163
V]]WQM>;m>C9H37OZDjNiT0
!s100 z93MB>87<aQA_?z8ffEAG3
R10
32
R11
!i10b 1
R12
R26
R27
!i113 1
R15
R16
