m255
K4
z2
!s11e vcom 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
dC:/DEE/Dimmer/FPGA
Eclk_generator
Z0 w1768150861
Z1 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z2 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 368
Z3 dC:/DEE/Dimmer/FPGA_PWM_top
Z4 8C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd
Z5 FC:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd
l0
L20 1
V1@L?e[dcRL0`WgX5ef^oB0
!s100 [XK?UZb9UP`J6jYeEbEEW3
Z6 OV;C;2020.1;71
32
Z7 !s110 1768254685
!i10b 1
Z8 !s108 1768254684.000000
Z9 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd|
Z10 !s107 C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd|
!i113 1
Z11 o-work work -2002 -explicit
Z12 tExplicit 1 CvgOpt 0
Aschematic
R1
R2
DEx4 work 13 clk_generator 0 22 1@L?e[dcRL0`WgX5ef^oB0
!i122 368
l60
L30 73
VC=N<`7mkjFX0?H<ZgFS323
!s100 0Jc0^Oc1Fo;mZH2mo@3Cj0
R6
32
R7
!i10b 1
R8
R9
R10
!i113 1
R11
R12
Ecomp_10bit
Z13 w1768009852
R1
R2
!i122 370
R3
Z14 8C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd
Z15 FC:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd
l0
Z16 L15 1
Vz@<XbT^=Ec=XRi<SoHM[A2
!s100 ?X>o480kSJ;fneTaEz:aW1
R6
32
R7
!i10b 1
Z17 !s108 1768254685.000000
Z18 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd|
Z19 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd|
!i113 1
R11
R12
Ahierarchical_structure
R1
R2
DEx4 work 10 comp_10bit 0 22 z@<XbT^=Ec=XRi<SoHM[A2
!i122 370
l36
L23 151
V5b6z8W6b0=[AJjRCSdRQQ2
!s100 kfdAi?37O<i[AdmaQW3dY1
R6
32
R7
!i10b 1
R17
R18
R19
!i113 1
R11
R12
Ecomp_1bit
Z20 w1750349063
R1
R2
!i122 369
R3
Z21 8C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd
Z22 FC:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd
l0
L11 1
VH?bbYFm9d9>5j]BD0WRX?2
!s100 ?L:0JBl3=32h_RIEJ:?m`0
R6
32
R7
!i10b 1
R17
Z23 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd|
Z24 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd|
!i113 1
R11
R12
Alogic_equations_sop
R1
R2
DEx4 work 9 comp_1bit 0 22 H?bbYFm9d9>5j]BD0WRX?2
!i122 369
l19
L18 9
VX^D;5AX4>U8WOe^3Y1oV:2
!s100 @bU41PZMj]oXzXbGz<EW]2
R6
32
R7
!i10b 1
R17
R23
R24
!i113 1
R11
R12
Ecounter_mod1024
Z25 w1767801005
Z26 DPx4 ieee 18 std_logic_unsigned 0 22 ;eZjO2D4ZDz<]0>8AL<ne1
Z27 DPx4 ieee 15 std_logic_arith 0 22 [G314=:2zXJ`VORJe1J@Z1
R1
R2
!i122 371
R3
Z28 8C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd
Z29 FC:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd
l0
Z30 L16 1
V_:@MlU9S@R[]9l@14IeD]2
!s100 2za9j>Gg=^J;13<X]ok:11
R6
32
R7
!i10b 1
R17
Z31 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd|
Z32 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd|
!i113 1
R11
R12
Afsm_like
R26
R27
R1
R2
DEx4 work 15 counter_mod1024 0 22 _:@MlU9S@R[]9l@14IeD]2
!i122 371
l40
L31 67
Vk9NFdNaILHhj67F3`?@Of0
!s100 8m=PESZ_ANInH4VifI3<Q1
R6
32
R7
!i10b 1
R17
R31
R32
!i113 1
R11
R12
Edata_reg_10bit
Z33 w1767984575
R1
R2
!i122 372
R3
Z34 8C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd
Z35 FC:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd
l0
R30
VHZ98ULCP?Hk[5Y@f3Y5Zh2
!s100 9S9<NlGaBjhDO8LOJ4kK@0
R6
32
R7
!i10b 1
R17
Z36 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd|
Z37 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd|
!i113 1
R11
R12
Afsm_like
R1
R2
DEx4 work 14 data_reg_10bit 0 22 HZ98ULCP?Hk[5Y@f3Y5Zh2
!i122 372
l36
L27 47
VQW=C?ed6:?VNRD_Aa44Nn0
!s100 7J]7[7bF^MGNMKmVM2oTj1
R6
32
R7
!i10b 1
R17
R36
R37
!i113 1
R11
R12
Edatapath
Z38 w1768148235
R1
R2
!i122 373
R3
Z39 8C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd
Z40 FC:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd
l0
R30
Vg3=ma3B>?lHY9dH<=_Q1]2
!s100 Un17m8FhJ`Dl^jA1OM7`K3
R6
32
R7
!i10b 1
R17
Z41 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd|
Z42 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd|
!i113 1
R11
R12
Astructure_planc2
R1
R2
DEx4 work 8 datapath 0 22 g3=ma3B>?lHY9dH<=_Q1]2
!i122 373
l69
L31 103
VZDoY>XLbQH^7IX?D]TBD91
!s100 6SLBF1BJU19gI?KfRMXzk1
R6
32
R7
!i10b 1
R17
R41
R42
!i113 1
R11
R12
Edebouncing_filter
Z43 w1768153903
R1
R2
!i122 374
R3
Z44 8C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd
Z45 FC:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd
l0
L18 1
VWAL`283<nnOUVHX2LcAYL2
!s100 6fPa_7glK9TF<GKP_;QdZ0
R6
32
R7
!i10b 1
R17
Z46 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd|
Z47 !s107 C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd|
!i113 1
R11
R12
Afsm_like
R1
R2
DEx4 work 17 debouncing_filter 0 22 WAL`283<nnOUVHX2LcAYL2
!i122 374
l35
L27 95
VikLdg8IB1YVzZP5^i:8IJ3
!s100 bc9n<NnfWRB>?0=2TYVgP3
R6
32
R7
!i10b 1
R17
R46
R47
!i113 1
R11
R12
Efreq_div_25
Z48 w1768149718
R26
R27
R1
R2
!i122 375
R3
Z49 8C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd
Z50 FC:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd
l0
Z51 L21 1
VKHlEOoX:8`5O5fG`7li<n0
!s100 =99oHned[1ND9WlCW`<[52
R6
32
Z52 !s110 1768254686
!i10b 1
Z53 !s108 1768254686.000000
Z54 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd|
Z55 !s107 C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd|
!i113 1
R11
R12
Afsm_like
R26
R27
R1
R2
DEx4 work 11 freq_div_25 0 22 KHlEOoX:8`5O5fG`7li<n0
!i122 375
l42
Z56 L27 48
Vce]CJ0M=>5z1cX4:Nco=U3
!s100 BkF]Az[O[I;D:MC[VR?d;0
R6
32
R52
!i10b 1
R53
R54
R55
!i113 1
R11
R12
Efreq_div_5000
Z57 w1768149866
R26
R27
R1
R2
!i122 376
R3
Z58 8C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd
Z59 FC:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd
l0
R51
VZT=kF9>RE?aELd<3RJCa?3
!s100 n7b^lk^C@@hDAV390kZ2H1
R6
32
R52
!i10b 1
R53
Z60 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd|
Z61 !s107 C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd|
!i113 1
R11
R12
Afsm_like
R26
R27
R1
R2
DEx4 work 13 freq_div_5000 0 22 ZT=kF9>RE?aELd<3RJCa?3
!i122 376
l42
R56
VTZl821ZMnKkRZ:PmMX[=]1
!s100 GCoVYOVWC0i12U4l?O8bi2
R6
32
R52
!i10b 1
R53
R60
R61
!i113 1
R11
R12
Efsm
Z62 w1768153163
R27
R26
R1
R2
!i122 377
R3
Z63 8C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd
Z64 FC:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd
l0
R30
VL5ohjDo?`NI^GF`6InJ@72
!s100 :YRIL>bfDc54`h5F?89PG3
R6
32
R52
!i10b 1
R53
Z65 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd|
Z66 !s107 C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd|
!i113 1
R11
R12
Aplan_c1
R27
R26
R1
R2
DEx4 work 3 fsm 0 22 L5ohjDo?`NI^GF`6InJ@72
!i122 377
l38
L29 94
VCL;P`IUCHhK;D=TILF:;^0
!s100 Y?6g_@iBVFE`CGbgmRkN^3
R6
32
R52
!i10b 1
R53
R65
R66
!i113 1
R11
R12
Epulse_gen
Z67 w1768166718
R1
R2
!i122 378
R3
Z68 8C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd
Z69 FC:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd
l0
R16
VWDYjazT^17A<bgeS^L6m13
!s100 UDAhjg;EbHzOD?TXM80hB3
R6
32
R52
!i10b 1
R53
Z70 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd|
Z71 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd|
!i113 1
R11
R12
Afsm_like
R1
R2
DEx4 work 9 pulse_gen 0 22 WDYjazT^17A<bgeS^L6m13
!i122 378
l31
L24 59
V;TH4O:h=;RR;]bF:jm7RE0
!s100 cWUk@aRk]eDMbc@FJnToL1
R6
32
R52
!i10b 1
R53
R70
R71
!i113 1
R11
R12
Epwm
Z72 w1768171727
R1
R2
!i122 379
R3
Z73 8C:/DEE/Dimmer/FPGA_PWM_top/PWM.vhd
Z74 FC:/DEE/Dimmer/FPGA_PWM_top/PWM.vhd
l0
Z75 L13 1
VgNU5MOglmoc>BaLEnfnM93
!s100 EI22_PcKKhngoW96VU^>g3
R6
32
R52
!i10b 1
R53
Z76 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/PWM.vhd|
Z77 !s107 C:/DEE/Dimmer/FPGA_PWM_top/PWM.vhd|
!i113 1
R11
R12
Adedicated_processor
R1
R2
DEx4 work 3 pwm 0 22 gNU5MOglmoc>BaLEnfnM93
!i122 379
l55
L25 63
VdfV2bkFhO`fIDhQRU39bO3
!s100 FU4AZlYOiN5okeJGCeAoC0
R6
32
R52
!i10b 1
R53
R76
R77
!i113 1
R11
R12
Epwm_top
Z78 w1768254261
R1
R2
!i122 380
R3
Z79 8C:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd
Z80 FC:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd
l0
R75
VaoShO<6T1cX9@KU6^NSd]1
!s100 [;P]]Go6YR?4HmHE@lYbN1
R6
32
R52
!i10b 1
R53
Z81 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd|
Z82 !s107 C:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd|
!i113 1
R11
R12
Adedicated_processor
R1
R2
DEx4 work 7 pwm_top 0 22 aoShO<6T1cX9@KU6^NSd]1
!i122 380
l72
L24 96
V6Zbc8hMeJFJ06YWWd_HgA2
!s100 GU9QOST4RdaNNKVL6nYJ;0
R6
32
R52
!i10b 1
R53
R81
R82
!i113 1
R11
R12
Epwm_top_vhd_tst
Z83 w1768254678
R1
R2
!i122 381
R3
Z84 8C:\DEE\Dimmer\FPGA_PWM_top\PWM_top_tb.vhd
Z85 FC:\DEE\Dimmer\FPGA_PWM_top\PWM_top_tb.vhd
l0
L31 1
V]G@DmR>YDe]JEBK_kLcmk0
!s100 <2FDlQ_Oef7:X>z:;>2Uz0
R6
32
Z86 !s110 1768254687
!i10b 1
R53
Z87 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:\DEE\Dimmer\FPGA_PWM_top\PWM_top_tb.vhd|
Z88 !s107 C:\DEE\Dimmer\FPGA_PWM_top\PWM_top_tb.vhd|
!i113 1
R11
R12
Apwm_top_arch
R1
R2
DEx4 work 15 pwm_top_vhd_tst 0 22 ]G@DmR>YDe]JEBK_kLcmk0
!i122 381
l62
L34 163
V:2CF<APBmBn^UQKoQ3_HU0
!s100 z93MB>87<aQA_?z8ffEAG3
R6
32
R86
!i10b 1
R53
R87
R88
!i113 1
R11
R12
Et_ff
Z89 w1750351290
R1
R2
!i122 382
R3
Z90 8C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd
Z91 FC:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd
l0
L10 1
VMdoD<Nh0KS5no1E0HKc;C0
!s100 ?VSgO=i=@PK_68aKbGj?D3
R6
32
R86
!i10b 1
Z92 !s108 1768254687.000000
Z93 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd|
Z94 !s107 C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd|
!i113 1
R11
R12
Afsm_like
R1
R2
Z95 DEx4 work 4 t_ff 0 22 MdoD<Nh0KS5no1E0HKc;C0
!i122 382
l32
Z96 L22 61
Z97 V]>]kR[O>7jT?KHB_3Xkzg3
Z98 !s100 bSL1R:;YCd2m3^1XVj2<:1
R6
32
R86
!i10b 1
R92
R93
R94
!i113 1
R11
R12
