m255
K4
z2
!s11e vcom 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/DEE/Dimmer/FPGA_PWM_top/simulation/modelsim
Eclk_generator
Z1 w1768150861
Z2 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3
Z3 DPx4 ieee 14 std_logic_1164 0 22 cVAk:aDinOX8^VGI1ekP<3
!i122 12
R0
Z4 8C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd
Z5 FC:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd
l0
L20 1
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!s100 [XK?UZb9UP`J6jYeEbEEW3
Z6 OV;C;2020.1;71
31
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!i10b 1
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Z9 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd|
!s107 C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd|
!i113 1
Z10 o-93 -work work
Z11 tExplicit 1 CvgOpt 0
Aschematic
R2
R3
DEx4 work 13 clk_generator 0 22 MY3maU[K03iJ2Y1?Z6_Rc1
!i122 12
l60
L30 73
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R6
31
R7
!i10b 1
R8
R9
Z12 !s107 C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd|
!i113 1
R10
R11
Ecomp_10bit
Z13 w1768009852
R2
R3
!i122 11
R0
Z14 8C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd
Z15 FC:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd
l0
Z16 L15 1
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R6
31
R7
!i10b 1
R8
Z17 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd|
Z18 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd|
!i113 1
R10
R11
Ahierarchical_structure
R2
R3
DEx4 work 10 comp_10bit 0 22 68o3zH3Qd?fzzbGehVo_41
!i122 11
l36
L23 151
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31
R7
!i10b 1
R8
R17
R18
!i113 1
R10
R11
Ecomp_1bit
Z19 w1750349063
R2
R3
!i122 10
R0
Z20 8C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd
Z21 FC:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd
l0
L11 1
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R6
31
R7
!i10b 1
R8
Z22 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd|
Z23 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd|
!i113 1
R10
R11
Alogic_equations_sop
R2
R3
DEx4 work 9 comp_1bit 0 22 CM8TE7UYU3nLlfXi42^Wg1
!i122 10
l19
L18 9
V00[D3<IbMM4Edg>dnZW<_3
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R6
31
R7
!i10b 1
R8
R22
R23
!i113 1
R10
R11
Ecounter_mod1024
Z24 w1767801005
Z25 DPx4 ieee 18 std_logic_unsigned 0 22 ;eZjO2D4ZDz<]0>8AL<ne1
Z26 DPx4 ieee 15 std_logic_arith 0 22 [G314=:2zXJ`VORJe1J@Z1
R2
R3
!i122 9
R0
Z27 8C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd
Z28 FC:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd
l0
Z29 L16 1
VSNI^EmQ1EDCo5VmdWom><3
!s100 2za9j>Gg=^J;13<X]ok:11
R6
31
R7
!i10b 1
R8
Z30 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd|
Z31 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd|
!i113 1
R10
R11
Afsm_like
R25
R26
R2
R3
DEx4 work 15 counter_mod1024 0 22 SNI^EmQ1EDCo5VmdWom><3
!i122 9
l40
L31 67
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!s100 8m=PESZ_ANInH4VifI3<Q1
R6
31
R7
!i10b 1
R8
R30
R31
!i113 1
R10
R11
Edata_reg_10bit
Z32 w1767984575
R2
R3
!i122 7
R0
Z33 8C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd
Z34 FC:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd
l0
R29
V6@<nLzeOH00=Nl0J8R>z12
!s100 9S9<NlGaBjhDO8LOJ4kK@0
R6
31
R7
!i10b 1
R8
Z35 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd|
Z36 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd|
!i113 1
R10
R11
Afsm_like
R2
R3
DEx4 work 14 data_reg_10bit 0 22 6@<nLzeOH00=Nl0J8R>z12
!i122 7
l36
L27 47
VQ8DjOielMVXb8PSgGaU1c3
!s100 7J]7[7bF^MGNMKmVM2oTj1
R6
31
R7
!i10b 1
R8
R35
R36
!i113 1
R10
R11
Edatapath
Z37 w1768148235
R2
R3
!i122 8
R0
Z38 8C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd
Z39 FC:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd
l0
R29
VAAJd[We3Gc>KSo:`3AUI@2
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R6
31
R7
!i10b 1
R8
Z40 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd|
Z41 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd|
!i113 1
R10
R11
Astructure_planc2
R2
R3
DEx4 work 8 datapath 0 22 AAJd[We3Gc>KSo:`3AUI@2
!i122 8
l69
L31 103
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R6
31
R7
!i10b 1
R8
R40
R41
!i113 1
R10
R11
Edebouncing_filter
Z42 w1768153903
R2
R3
!i122 1
R0
Z43 8C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd
Z44 FC:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd
l0
L18 1
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R6
31
Z45 !s110 1768167739
!i10b 1
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Z47 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd|
Z48 !s107 C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd|
!i113 1
R10
R11
Afsm_like
R2
R3
DEx4 work 17 debouncing_filter 0 22 aOo1MP;nMW?n>;8JjK95J0
!i122 1
l35
L27 95
V05@@?PGaJGDcn;c<6;FfB0
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R6
31
R45
!i10b 1
R46
R47
R48
!i113 1
R10
R11
Efreq_div_25
Z49 w1768149718
R25
R26
R2
R3
!i122 6
R0
Z50 8C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd
Z51 FC:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd
l0
Z52 L21 1
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R6
31
R7
!i10b 1
R8
Z53 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd|
Z54 !s107 C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd|
!i113 1
R10
R11
Afsm_like
R25
R26
R2
R3
DEx4 work 11 freq_div_25 0 22 KJF;omlN2@CSZTD;P]gY51
!i122 6
l42
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!s100 BkF]Az[O[I;D:MC[VR?d;0
R6
31
R7
!i10b 1
R8
R53
R54
!i113 1
R10
R11
Efreq_div_5000
Z56 w1768149866
R25
R26
R2
R3
!i122 5
R0
Z57 8C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd
Z58 FC:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd
l0
R52
VYE_iCY[F^5^Vzdfc<@DhO2
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R6
31
R45
!i10b 1
R46
Z59 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd|
Z60 !s107 C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd|
!i113 1
R10
R11
Afsm_like
R25
R26
R2
R3
DEx4 work 13 freq_div_5000 0 22 YE_iCY[F^5^Vzdfc<@DhO2
!i122 5
l42
R55
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!s100 GCoVYOVWC0i12U4l?O8bi2
R6
31
R45
!i10b 1
R46
R59
R60
!i113 1
R10
R11
Efsm
Z61 w1768153163
R26
R25
R2
R3
!i122 4
R0
Z62 8C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd
Z63 FC:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd
l0
R29
V6Slo9gnag9eOn`6NigT[;1
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R6
31
R45
!i10b 1
R46
Z64 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd|
Z65 !s107 C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd|
!i113 1
R10
R11
Aplan_c1
R26
R25
R2
R3
DEx4 work 3 fsm 0 22 6Slo9gnag9eOn`6NigT[;1
!i122 4
l38
L29 94
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R6
31
R45
!i10b 1
R46
R64
R65
!i113 1
R10
R11
Epulse_gen
Z66 w1768166718
R2
R3
!i122 0
R0
Z67 8C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd
Z68 FC:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd
l0
R16
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R6
31
R45
!i10b 1
R46
Z69 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd|
Z70 !s107 C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd|
!i113 1
R10
R11
Afsm_like
R2
R3
DEx4 work 9 pulse_gen 0 22 UhRRBlD@IjZOTUd27TbWY3
!i122 0
l31
L24 59
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R6
31
R45
!i10b 1
R46
R69
R70
!i113 1
R10
R11
Epwm_top
Z71 w1768166749
R2
R3
!i122 3
R0
Z72 8C:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd
Z73 FC:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd
l0
L13 1
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R6
31
R45
!i10b 1
R46
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Z75 !s107 C:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd|
!i113 1
R10
R11
Adedicated_processor
R2
R3
DEx4 work 7 pwm_top 0 22 lEhfJN::cE6`n^DPeiMSJ3
!i122 3
l91
L26 128
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R6
31
R45
!i10b 1
R46
R74
R75
!i113 1
R10
R11
Et_ff
Z76 w1750351290
R2
R3
!i122 2
R0
Z77 8C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd
Z78 FC:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd
l0
L10 1
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R6
31
R45
!i10b 1
R46
Z79 !s90 -reportprogress|300|-93|-work|work|C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd|
Z80 !s107 C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd|
!i113 1
R10
R11
Afsm_like
R2
R3
DEx4 work 4 t_ff 0 22 DZhX<XXQB:]GWYlGLe[?_2
!i122 2
l32
L22 61
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R6
31
R45
!i10b 1
R46
R79
R80
!i113 1
R10
R11
