# Reading pref.tcl
# do PWM_top_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:19 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/Pulse_gen.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Pulse_gen
# -- Compiling architecture FSM_like of Pulse_gen
# End time: 22:42:19 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:19 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/debouncing_filter.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity debouncing_filter
# -- Compiling architecture FSM_like of debouncing_filter
# End time: 22:42:19 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:19 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/T_FF.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity T_FF
# -- Compiling architecture FSM_like of T_FF
# End time: 22:42:19 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:19 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/PWM_top.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity PWM_top
# -- Compiling architecture dedicated_processor of PWM_top
# End time: 22:42:19 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:19 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/FSM.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity FSM
# -- Compiling architecture plan_C1 of FSM
# End time: 22:42:19 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:19 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/freq_div_5000.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity freq_div_5000
# -- Compiling architecture FSM_like of freq_div_5000
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:20 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/freq_div_25.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity freq_div_25
# -- Compiling architecture FSM_like of freq_div_25
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:20 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/Data_reg_10bit.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Data_Reg_10bit
# -- Compiling architecture FSM_like of Data_Reg_10bit
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:20 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/Datapath.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Datapath
# -- Compiling architecture structure_planC2 of Datapath
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:20 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/Counter_mod1024.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity Counter_mod1024
# -- Compiling architecture FSM_like of Counter_mod1024
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:20 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/Comp_1bit.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Comp_1bit
# -- Compiling architecture logic_equations_SoP of Comp_1bit
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:20 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/Comp_10bit.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Comp_10bit
# -- Compiling architecture hierarchical_structure of Comp_10bit
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work work {C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:42:20 on Jan 11,2026
# vcom -reportprogress 300 -93 -work work C:/DEE/Dimmer/FPGA_PWM_top/CLK_Generator.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity CLK_Generator
# -- Compiling architecture schematic of CLK_Generator
# End time: 22:42:20 on Jan 11,2026, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# reading C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini
# Loading project PWM_top_functional_sim
