﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC
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## P1 and P4 tutorial: electrical characteristics of digital circuits

Voltages, power consumption and propagation time

The world of digital electronic technologies is formidable and a huge industry. It is also a high-end research area. Here in this introductory CSD subject our aim is very simple, let us discover basic features of logic gates and programmable devices such as voltages, power consumption and gate delays.

This is the unit on programmable devices (PLD)

This is a list of classic chips in conventional technologies: CMOS, TTL, LSTTL, HCT, etc.

'1' and '0' logic symbols and voltage levels (V), push-buttons and LED

Buttons and switches: How to connect push-buttons and switches to chip inputs to generate '1' and '0'?

Voltages and logic levels Which voltages are interpreted as a '0' and a '1' at the input or at the output of a logic gate? This is Circuit_W  to play with buttons in Proteus.

Standard logic gates and chip references. Standard symbols: traditional and ANSI. Commom logic families (1), (2).

 Fig. 1. Definition of the high and low noise margins (souce ref.). Technology 74LS (for instance, chip 74LS04) or CMOS 4069.

Some basic ideas (1) to start: voltage values, noise margins, power rails, etc. These are typical datasheets (LS-TTL, CMOS).

Driving LED: How to drive LED from logic gates? rec. This (2) is a circuit to play with LED and to observe how when a logic gate is sinking too much current voltage levels are degraded.

Typical LED datasheet.

Power  consumption (~pW,~nW, ~μW)

• Static power (PS) dissipation is the power consumed when the output or input is not changing. Normally, static power dissipation is caused by leakage current. CMOS technology has very low PS.

• Dynamic power  (PD) is the power consumed during output and input transitions when the signal level changes and thus the circuit is processing . It is caused by the switching current, which charges and discharges parasitic capacitances. In CMOS technology, it is also caused by the short-circuit current when both NMOS and PMOS transistors are momentarily ON at the same time in signal edges. The higher the  frequency of operation the higher is the PD.

Propagation times and computation speed (~ns, ~MHz, ~GHz)

Gate delay or propagation time associated to a logic gate. Some basic notes.

Simulation of a CMOS inverter gate 4069 in Proteus.

 Fig. 2. Example of a CMOS inverter type 4069 simulated in Proteus.

Simulation of a 74LS inverter gate 74LS04 in Proteus.

Example of a simple programmable logic device sPLD solving a function. Maximum speed of operation.

Example of a CPLD electrical characteristics.

Example of a FPGA electrical characteristics.

Tri-state gates

Definition and how it works.

Example of a tri-state gate using CMOS technology.

Example of a tri-state buffer gate implementation in VHDL in this RAM tutorial.

Open collector/drain gates

Definition and how it works.

Other materials of interest

Databook on logic circuits from Texas Instruments