upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

2021Q1 - List of preparatory laboratory assignments (PLA) and projects

NOTE: VHDL EDA in use: Intel Quartus Prime Lite and ModelSim Intel Edition

PLA1 analysis and design of logic circuit 

 Assigment. Analyse Circuit_T and design equivalents Circuit_2 and Circuit_4. Due date: October 9.


PLA2 Designing an standard logic circuit (structural plan A and behavioural plan B)

 Design ..... Due date:


PLA3_4 on the design of arithmetic circuits and hierarchical design (plan C2). Propagation time measurement


PLA5_6 on 1-bit memory cells and FSM



PLA7_8 on FSM, standard sequencial blocks and dedicated processors


NOTE: IDE in use: Microchip MPLABX, XC8 compiler and Proteus VSM

PLA9_10 on microcontroller circuits


Final P_Ch3, report + oral presentation


Other similar projects and PLA from former courses

- 1921Q1

- 1920Q2